Clock Signal Adjustment for Power Noise Reduction
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Solution Overview
Problem
Multi-frequency clocking in synchronous environments leads to noisy power signals due to fluctuations in power consumption, negatively impacting the performance of application-specific integrated circuits (ASICs) when multiple domains share a common power and clock source.
Innovation Solution
A method and device that adjust clock signals across different processing domains to minimize the impact of power consumption changes by determining and implementing sub-clock pulse schemes that offset changes in power draw, thereby reducing noise in the power signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If multi-frequency clocking is implemented to save dynamic power, then power consumption is reduced, but power signal noise increases
Solution Approach 1:
The patent combines multiple clock domains into a single synchronous clocking structure, where all domains share a common clock source. This merging eliminates the power draw fluctuations caused by independent multi-frequency clocking while preserving power savings through coordinated clock gating across domains.
Solution Approach 2:
The patent converts the harmful effect of power draw fluctuations into a benefit by using the clock signal itself to synchronize power consumption patterns across domains. The coordinated clocking ensures that when one domain draws power, others compensate, transforming the noise problem into a power optimization opportunity.
2Productivity
If clock frequency is varied across domains to meet processing needs, then processing performance is improved, but power signal stability deteriorates
Solution Approach 1:
The patent implements dynamic clock gating within a synchronous framework, allowing each domain to dynamically enable or disable clock cycles based on processing needs while maintaining overall synchronization. This dynamic approach preserves processing performance while stabilizing power signal through coordinated domain behavior.
Solution Approach 2:
The patent changes the clocking parameter from fixed multi-frequency to variable-frequency synchronous clocking with coordination. Each domain can adjust its effective clock frequency through gating while the underlying synchronous structure maintains power signal stability through coordinated parameter changes across all domains.
3Use of energy by stationary object
If domains skip clock pulses to reduce power draw, then current consumption is reduced, but power delivery disturbance increases
Solution Approach 1:
The patent implements feedback mechanisms where clock gating decisions in one domain are coordinated with other domains based on system-wide power and performance requirements. This feedback ensures that when domains skip clock pulses, the coordination minimizes cumulative power draw disturbances on the shared power delivery network.
Data Source
AI summary
A device and method of operating a synchronous frequency processing environment served by a common power source and common clock source. The method includes operating the processing environment to have a first power consumption. The method further includes determining a first synchronous frequency processing domain within the processing environment where it is desired to implement a first clock frequency alteration in a clock signal for the first synchronous frequency processing domain. The first clock frequency alteration generates an associated first alteration in a power consumption from the first synchronous frequency processing domain. The method further includes determining a second clock frequency alteration to a clock signal for a second synchronous frequency processing domain of the processing environment. The second clock frequency alteration is determined so as to reduce a change in the first power consumption caused by the first alteration in power consumption.