Clock Signal Encoding for Ancillary Data in High-Speed Interfaces
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Solution Overview
Problem
In high data-rate transmission systems, transmitting ancillary information, such as control signals, can compromise high-speed data transfer performance and increase costs due to the need for additional signal lines, which is undesirable for minimizing device size and maintaining efficiency.
Innovation Solution
A data transmission system where a data transmitter encodes ancillary data into a clock or frame signal, allowing additional information to be transmitted without increasing the number of data lines by using the location of the falling-edge within a data frame to convey logic states, which can be decoded by the receiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ancillary information is transmitted over existing data lines, then data transmission capacity is utilized, but high-speed data transfer performance is greatly sacrificed
Solution Approach 1:
The clock signal is made multi-functional by encoding both synchronization timing information and ancillary data within the same signal. The data encoder modifies the clock signal to include ancillary information while maintaining its synchronization function, allowing a single signal to serve dual purposes without compromising data transfer performance
Solution Approach 2:
The invention merges the transmission of ancillary information with the existing clock signal transmission. By combining control signals with the clock signal that already traverses the data link, the system utilizes existing infrastructure without adding separate transmission channels that would interfere with high-speed data transfer
2Loss of information
If one or more signal lines are added between data transmitter and receiver, then ancillary information can be transmitted, but additional cost and spatial requirements are violated
Solution Approach 1:
Existing clock signal lines are made universal by enabling them to carry both timing synchronization and ancillary information. This eliminates the need for separate dedicated signal lines for control information, thereby reducing device complexity and spatial requirements while maintaining full functionality
Solution Approach 2:
The clock signal serves itself dual purposes by simultaneously providing synchronization timing and carrying ancillary data. The existing infrastructure is made self-sufficient by encoding additional information within the clock signal itself, eliminating the need for external additional signal lines
Data Source
AI summary
One embodiment of the present invention includes a data transmission system. The system comprises a data transmitter that provides a plurality of data bits over at least one data line. The data transmitter comprises a clock that provides a clock signal associated with timing for latching the plurality of data bits and a data encoder configured to encode error data associated with the data transmission system in the clock signal.