Clock Signal Circuit for Synchronized Switched-Capacitor Chopping
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Solution Overview
Problem
In delta-sigma type A/D converters using switched capacitor circuits, the ON/OFF timing of the internal switch and the chopping switch are often mismatched, leading to potential output errors due to the lack of synchronized edge signals for controlling these switches.
Innovation Solution
A clock signal generation circuit that includes first and second synchronous clock circuits to generate synchronized clock signals for the switched capacitor circuit and the chopping function unit, with an edge signal generation circuit producing rise and fall edge signals to ensure synchronized edge timings for both, allowing flexible frequency setting and synchronized ON/OFF timing control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate clock signals are used for switched capacitor circuit and chopping function unit, then frequency flexibility is improved, but timing synchronization deteriorates
Solution Approach 1:
The clock signal generation is segmented into multiple independent sources: a first clock signal for the switched capacitor circuit and a second clock signal for the chopping function unit. This allows each circuit to operate at its optimal frequency independently, achieving frequency flexibility while maintaining timing synchronization through separate but coordinated clock generators.
Solution Approach 2:
An edge signal generation circuit acts as an intermediary between the clock signals and the switch control. This circuit generates precise edge signals that coordinate the ON/OFF timing of both the internal switch and chopping switch, ensuring timing synchronization even when clock frequencies differ.
2Reliability
If merged timing signals are used for internal switch and chopping switch, then timing synchronization is improved, but frequency flexibility deteriorates
Solution Approach 1:
The timing control is segmented into separate clock signal paths for the internal switch and chopping switch. Each path can be independently configured with different frequencies, allowing the system to maintain timing synchronization within each path while providing overall frequency flexibility across the entire system.
Solution Approach 2:
The edge signal generation circuit serves multiple functions: it generates edge signals for both the internal switch control and the chopping switch control. This multi-functional component ensures timing synchronization across different frequency domains, allowing a single circuit to handle multiple timing requirements with different frequencies.
3Measurement precision
If synchronized edge signals are generated for both circuits, then output error is reduced, but circuit complexity increases
Solution Approach 1:
The edge signal generation circuit serves as an intermediary that receives clock signals and generates precisely timed edge signals for both the internal switch and chopping switch. This centralized edge generation approach ensures synchronized timing without requiring complex interconnections between separate control circuits, thereby reducing overall system complexity while maintaining high output accuracy.
Data Source
AI summary
A clock signal generation circuit for a switched capacitor circuit with a chopping function unit includes: first and second synchronous clock circuits that generate first and second synchronous clock signals, respectively; an edge signal generation circuit that generates one or more rise and fall edge signals by delaying the first synchronous clock signal; a first clock generator that generate a first clock signal group for driving the switched capacitor circuit; and a second clock generator that generates a second clock signal group for driving the chopping function unit. Frequencies of the first and second clock signal groups are respectively defined by the first and second synchronous clock circuits. Rise and fall edges of the first and second clock signal groups are defined by the edge signal generation circuit.