Clock Signal Conditioning Circuit for GOA Stage Transfer Stability
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Solution Overview
Problem
In current liquid crystal panel display technology, abnormal conditions such as no signal output from a CK clock signal can lead to abnormal GOA stage transfers, resulting in display abnormalities.
Innovation Solution
A clock signal conditioning circuit and method that includes a signal conversion circuit and a delay processing circuit. The circuit converts the clock signal and performs delay processing on the N-th clock signal when the voltage amplitude of the converted signal falls within a turn-on threshold range, ensuring the delayed clock signal has the same timing as the (N+1)-th clock signal, thereby maintaining normal GOA stage transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GOA stage shift is used for line scanning drive, then the bonding process of external IC is reduced and product cost is reduced, but if one of the CK clock signals is abnormal (no signal output), then GOA stage transfer becomes abnormal and display abnormality occurs
Solution Approach 1:
The patent applies preliminary action by detecting the clock signal status in advance through the signal conversion circuit before it reaches the GOA drive circuit. When an abnormal condition is detected (no signal output), the system proactively compensates by using the previous stage's clock signal with delay processing, preventing the display abnormality from occurring in the first place.
Solution Approach 2:
The patent introduces an intermediary mechanism - the signal conversion circuit and delay processing circuit - that mediates between the clock signal source and the GOA drive circuit. This intermediary detects signal abnormalities and provides compensation signals, ensuring continuous normal operation of the GOA stage transfer even when the original clock signal fails.
2Ease of operation
If multiple CK clock signals are used for enabling line scanning, then the line scanning drive is enabled, but if one clock signal output is abnormal, then the GOA stage transfer is abnormal
Solution Approach 1:
The patent implements feedback by using the output status of the (N+1)-th clock signal to control the selection and processing of the N-th clock signal. The signal conversion circuit converts the clock signal and the delay processing circuit adjusts the timing based on the detected signal status, creating a closed-loop feedback system that ensures reliable GOA stage transfer.
Solution Approach 2:
The patent applies parameter changes by modifying the timing parameters of the clock signal through delay processing. When the (N+1)-th clock signal is abnormal, the system changes the timing of the N-th clock signal by introducing a preset interval delay, transforming it into a delayed clock signal that synchronizes with the expected timing of the (N+1)-th signal.
Data Source
AI summary
The present disclosure relates to a circuit and a method for conditioning a clock signal, display panel, and display device. The circuit includes a signal conversion circuit and a delay processing circuit; when a voltage amplitude of the converted electrical signal falls within a turn-on threshold range, the delay processing circuit receives the N-th clock signal transmitted from the N-th clock signal output terminal, and performs delay processing on the N-th clock signal, so as to avoid occurrence of GOA-stage transfer abnormality when one of the plurality of CK clock signals is in an abnormal condition that no signal is output.