Clock Signal Generation by Digital Counting for Fast Frequency Synthesis
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Solution Overview
Problem
Conventional frequency synthesizers require large capacitors to change low-frequency input signals into output signals, which is impractical for integration with semiconductor technology and results in long phase-locking times when using digital phase locked loops.
Innovation Solution
A clock signal generating circuit that counts input clock signal periods using a reference clock, dividing the count signal to set a reference period and distributing the remainder as a modulation period, allowing for frequency change without large capacitors and reducing phase-locking time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large capacitor is used in the loop filter to change low-frequency input signals into output signals, then the frequency bandwidth is improved, but the device size and integration difficulty increase
Solution Approach 1:
The patent replaces the conventional analog loop filter capacitor with a digital frequency counter and divider system. Instead of using a large physical capacitor to handle low-frequency signals, the invention uses digital counting and division circuits that can process a wide range of input frequencies without requiring large passive components, thereby enabling semiconductor integration while maintaining broad frequency adaptability
Solution Approach 2:
The patent changes the operating parameters by using a high-frequency reference clock (e.g., 100 MHz) and digital division ratios to achieve frequency synthesis. By changing from analog capacitor-based filtering to digital frequency division, the system can handle low-frequency input signals (down to 50 Hz) without requiring large capacitors, thus resolving the contradiction between frequency bandwidth and device size
2Ease of manufacture
If a digital phase locked loop is used to avoid large capacitors, then the device integration is improved, but the phase-locking time increases significantly
Solution Approach 1:
The patent implements preliminary frequency measurement by using a frequency counter that counts reference clock cycles during one period of the input signal before generating the divided output frequency. This preliminary counting action allows the system to quickly determine the input frequency and establish the correct division ratio, significantly reducing the phase-locking time compared to conventional digital PLLs that require multiple signal periods to lock
Solution Approach 2:
The patent uses a reference clock signal as a template or copy to measure and replicate the timing characteristics of the input signal. By counting reference clock cycles that correspond to one period of the input signal, the system creates a digital representation of the input frequency, enabling rapid frequency synthesis without requiring long observation periods
Data Source
AI summary
The present invention relates to a clock signal generating circuit and a power supply including the same. The present invention includes: a counter for counting one period of an input clock signal by using a reference clock signal, and generating a count signal; and a clock signal generator for receiving the count signal and the reference clock signal, dividing the count signal to generate a quotient and a remainder, setting the quotient as a reference period of an output clock signal, and distributing and disposing the remainder to the output clock signal with a plurality of periods occurring for one period of the input clock signal.