Clock Signal Driver Amplitude Equalization for Display Devices
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Solution Overview
Problem
Display devices face image quality degradation due to amplitude differences in clock signals caused by unequal resistances in clock lines, leading to undesirable transverse line patterns.
Innovation Solution
A display device with a clock signal driver that compares feedback clock signals and controls their amplitudes using a multiplexer (MUX) control signal, attenuating signals through resistor banks to equalize current or voltage levels between clock lines, thereby reducing resistance imbalances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If clock signals are applied through clock lines with unequal resistances, then the display device can operate with multiple pixels, but amplitude differences occur between clock signals causing transverse line patterns
Solution Approach 1:
The patent applies local quality by introducing compensation circuits at specific locations where amplitude differences occur. These circuits provide localized amplitude adjustment to clock signals based on the actual resistance characteristics of individual clock lines, thereby compensating for manufacturing variations in clock line resistances and eliminating transverse line patterns while maintaining uniform image quality across all pixels
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the amplitude parameter of clock signals through compensation circuits. By measuring the actual amplitude of clock signals and modifying them in real-time, the system compensates for resistance differences in clock lines, ensuring uniform amplitude delivery to all gate drivers despite variations in clock line characteristics
2Device complexity
If clock line resistances are made unequal to simplify routing, then device complexity is reduced, but amplitude differences cause transverse line patterns
Solution Approach 1:
The patent converts the harmful effect of clock line resistance differences into a beneficial measurement signal. By using the amplitude differences caused by resistance variations as feedback information, the compensation circuits can calculate and apply appropriate correction amounts, thereby transforming the originally harmful resistance inequalities into useful data for achieving uniform clock signal amplitudes across all pixels
3Manufacturing precision
If amplitude compensation circuits are added to equalize clock signals, then transverse line patterns are prevented, but device complexity increases
Solution Approach 1:
The patent implements self-service by designing compensation circuits that automatically measure and correct their own operating parameters. The circuits monitor the amplitude of clock signals they generate and autonomously adjust compensation amounts based on measured values, eliminating the need for external calibration or manual intervention while maintaining uniform image quality across the display
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces amplitude differences between clock signals, preventing image defects like transverse line patterns and maintaining consistent image quality across the display.
Implementation Method 1
unequal resistances in clock lines
Implementation Method 2
a first resistor bank including a plurality of first resistors
Data Source
AI summary
A display device may include: a plurality of pixels; a gate driver that receives clock signals and generates and applies a plurality of gate signals to a respective plurality of gate lines connected to the plurality of pixels; and a clock signal driver. The clock signal driver may output the clock signals and receive feedback clock signals derived from the clock signals, compare the feedback clock signals, and control amplitudes of the clock signals so that an amplitude difference between the feedback clock signals is less than a threshold.