Clock Signal Analysis for Evaluating Voltage Droop Mitigation
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Solution Overview
Problem
Computer circuits, such as CPUs and GPUs, experience performance issues due to voltage droops caused by large changes in current required from the power delivery network (PDN).
Innovation Solution
A method and circuit for evaluating the performance of a droop mitigation scheme, which involves receiving a clock output signal generated using the droop mitigation scheme, analyzing it to generate an output indicating performance, and optionally adjusting the scheme based on performance indicators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the frequency of the clock output signal is adjusted in response to a droop event, then the performance and reliability of computer circuits are improved, but the complexity of the clock circuit increases due to multiple clock sources and selection mechanisms
Solution Approach 1:
The patent changes the frequency parameter of the clock signal dynamically. A nominal clock signal operates at a first frequency during normal conditions, while a fallback clock signal operates at a second frequency when voltage droop is detected. This parameter change allows the system to adapt to voltage fluctuations without requiring complete circuit redesign, thereby improving reliability while managing complexity through controlled frequency variation.
Solution Approach 2:
The clock circuit transitions from a static single-frequency design to a dynamic multi-frequency system. The droop mitigation scheme enables real-time switching between nominal and fallback clock frequencies based on voltage conditions. This dynamic adaptation allows the circuit to respond to changing power delivery conditions, improving reliability while the switching mechanism manages the inherent complexity through automated control.
2Adaptability or versatility
If a droop mitigation scheme with multiple clock sources is implemented, then the ability to handle voltage droop events is improved, but the device complexity and power consumption increase
Solution Approach 1:
The system prepares multiple clock sources (nominal and fallback) in advance before voltage droop events occur. The fallback clock signal is pre-configured at a different frequency to be ready for immediate activation. This preliminary preparation enables rapid response to droop events without requiring complex real-time generation of alternative clock signals, thereby improving adaptability while managing complexity through pre-established configurations.
Solution Approach 2:
The droop mitigation scheme introduces an intermediary control mechanism that manages the switching between nominal and fallback clock signals. This intermediary layer handles the complexity of coordinating multiple clock sources, allowing the main system to benefit from enhanced droop handling capability without directly managing the full complexity of the multi-clock architecture. The intermediary absorbs the complexity burden while providing simplified interfaces to the rest of the system.
Data Source
AI summary
The present techniques relate to droop mitigation scheme and there is disclosed a method of evaluating the performance of a droop mitigation scheme, wherein the method is carried out at a circuit, the method comprising: receiving a clock output signal, wherein the droop mitigation scheme has been used to generate the clock output signal; and analysing the clock output signal to generate an output, wherein the output provides an indication of the performance of the droop mitigation scheme.