Clock Signal Integrity Checking for Error Injection Detection
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Solution Overview
Problem
Advanced hacking methods, such as error injection, can compromise the integrity of clock signals in secured integrated circuits by introducing parasitic accelerations, leading to errors in data transfer and frequency deviations, which existing redundancy methods struggle to detect efficiently without significant resource overhead.
Innovation Solution
A method and device that detect the acceleration of a logic signal by using control bits with specific inversion delays to identify anomalies in the clock signal, producing an asynchronous error signal that filters tolerated synchronization errors and generates a synchronous error signal to detect accelerations before they cause data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the clock signal frequency is increased to improve processing speed, then productivity increases, but the circuit becomes vulnerable to error injection attacks due to asynchronous data propagation
Solution Approach 1:
The patent applies preliminary action by detecting clock signal accelerations before they can cause data propagation errors. The detection circuit monitors for premature clock edges that would trigger flip-flops before data is ready, and generates an error signal to prevent the harmful effect from occurring in the first place
Solution Approach 2:
The patent implements feedback by using the output of the detection circuit to generate an error signal that feeds back to the synchronous circuit. This feedback mechanism allows the system to respond to detected accelerations by preventing erroneous data propagation, thus maintaining reliability even at high frequencies
2Reliability
If error detection mechanisms are added to improve security, then reliability against attacks improves, but device complexity increases
Solution Approach 1:
The patent uses an intermediary detection circuit that sits between the clock signal source and the synchronous modules. This intermediary monitors the clock signal for accelerations and generates control signals to prevent erroneous operations, adding security without requiring modification of the core synchronous modules
Solution Approach 2:
The patent changes the monitoring approach from detecting data errors (which would require complex comparison circuits) to detecting clock signal parameter changes (accelerations). By monitoring the timing parameter of the clock signal itself, the system achieves security with simpler logic that only needs to detect premature edge transitions
Data Source
AI summary
A device and a method detect an acceleration of a logic signal expressed by a closeness, beyond a closeness threshold, of at least two variation edges of the logic signal. A first control bit and a second control bit are provided. At each edge of the logic signal, the value of the first control bit is inverted after a first delay and the value of the second control bit is inverted after a second delay. An acceleration is detected when the two control bits have at the same time their respective initial values or their respective inverted initial values. Application is in particular but not exclusively to the detection of error injections in a secured integrated circuit.