Clock Signal Generator Circuit with Dynamic Frequency Spreading
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Solution Overview
Problem
Conventional clock signal generator circuits face challenges in reducing circuit size while maintaining voltage boosting ability and are unable to effectively manage high-frequency noises, particularly in vehicle applications, due to their large size and limited high-speed operation capabilities.
Innovation Solution
A clock signal generator circuit that includes a CR oscillator part and a frequency varying part, utilizing a capacitor and resistive elements with switchable buffers to vary the resistance value and frequency of the clock signal, allowing for high-speed operation without increasing circuit size and reducing high-frequency noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the frequency of the clock signal is increased to reduce circuit size, then the voltage boosting ability is maintained, but high frequency noises are generated
Solution Approach 1:
The patent applies dynamics by making the resistance value variable rather than fixed. The frequency varying part changes the resistance value of the resistor dynamically in response to operation part signals, causing the clock signal frequency to vary over time. This dynamic frequency variation spreads the energy spectrum, reducing peak noise levels while maintaining the high frequency operation needed for small circuit size.
Solution Approach 2:
The patent changes the parameter of resistance value to achieve frequency spreading. By varying the resistance value of the resistor through the frequency varying part, the clock signal frequency is modulated, which spreads the spectral energy and reduces high frequency noise peaks. This allows the circuit to operate at high frequencies for size reduction while meeting noise standards.
2Object-generated harmful factors
If a conventional frequency spreading circuit is used to reduce high frequency noises, then noise is spread, but the circuit scale increases
Solution Approach 1:
The patent merges the frequency spreading function into the existing clock signal generation circuitry. The frequency varying part is integrated with the CR oscillator part, sharing common components like the capacitor and utilizing the existing operational amplifier. This combination achieves frequency spreading without adding a separate, large-sized frequency spreading circuit, thus reducing overall circuit scale.
Solution Approach 2:
The operational amplifier and capacitor in the CR oscillator part serve multiple functions: they generate the clock signal and simultaneously enable frequency spreading through the frequency varying part. The resistor also serves dual purposes as both the timing element for frequency generation and the variable element for frequency modulation. This multi-functionality reduces the need for additional dedicated noise reduction circuitry.
3Object-generated harmful factors
If a comparator-based frequency spreading circuit is used, then frequency spreading is achieved, but high-speed operation capability is reduced
Solution Approach 1:
The patent replaces the mechanical/comparator-based switching mechanism with an electronic operational amplifier-based system. The frequency varying part uses the operational amplifier to control the resistance variation, eliminating the need for comparators and their associated stabilization periods. This substitution enables high-speed operation beyond 1 MHz while achieving frequency spreading for noise reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables frequency spreading without increasing circuit scale, allowing for high-speed operation beyond 1 MHz and reducing high-frequency noise levels, making it suitable for small-sized devices and compliant with vehicle standards.
Implementation Method 1
a CR oscillator part (14), which includes a capacitor (C1) and a resistor (23) and outputs a clock signal (CLK) having a frequency corresponding to a time constant determined by the capacitor (C1) and the resistor (23)
Implementation Method 2
The frequency varying part includes plural buffers (6 to 11) having input terminals connected in common and output terminals connected to other terminals of the resistive elements (R1 to R5), respectively, and are switchable between a normal operation state and a high impedance state
Data Source
AI summary
A clock signal generator circuit includes a CR oscillator part, which outputs a clock signal having a frequency corresponding to a time constant determined by a capacitor and a resistor, and a frequency varying part. The frequency varying part includes a counter for performing a counting operation and varies a frequency of the clock signal by varying a resistance value of the resistor in correspondence to a count value of the counter. The resistor of the CR oscillator part includes plural resistive elements, one terminal of which are connected to a common node. The frequency varying part includes tri-state buffers, input terminals of which are connected in common and output terminals of which are connected to other terminals of the resistive elements, respectively, and varies the resistance value of the resistor by switching over states of the buffers in correspondence to the count value.