Clock Signal Line Dual-Layer Structure for RC Delay Reduction
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Solution Overview
Problem
The delay of clock signals in liquid crystal display devices due to parasitic capacitance between clock signal lines and adjacent signal lines leads to reduced charging rates, causing defects in image quality such as color mixing or crosstalk, especially as the resolution or size of the panel increases.
Innovation Solution
The implementation of clock signal lines with a dual-layer conductive structure, where a first conductive line is formed in the same layer as a light blocking layer and a second conductive line overlaps the first, connected through a connector, reduces the resistance and parasitic capacitance, thereby minimizing RC delay and improving signal delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the resolution or size of the liquid crystal panel is increased, then the display quality is improved, but the RC delay of clock signals increases due to parasitic capacitance between clock signal lines and adjacent signal lines
Solution Approach 1:
The clock signal line is divided into multiple segments with different widths along its length. The width of the clock signal line is varied to control the parasitic capacitance at different positions, thereby reducing the overall RC delay while maintaining display quality.
Solution Approach 2:
Different sections of the clock signal line are given different properties (widths) according to their specific needs. Sections with higher parasitic capacitance are made narrower to reduce capacitance, while sections requiring stronger signal drive are made wider, optimizing the balance between signal integrity and delay reduction.
2Loss of time
If the width of clock signal lines is increased to reduce resistance, then the RC delay is reduced, but the peripheral area occupied by clock signal lines increases
Solution Approach 1:
The clock signal line width is segmented into multiple zones with different widths. By strategically placing narrower sections where high resistance is not critical and wider sections where signal integrity is paramount, the overall area is reduced while maintaining acceptable RC delay characteristics.
Solution Approach 2:
The width parameter of the clock signal line is dynamically changed along its length rather than maintaining a uniform width. This allows optimization of the product of resistance and capacitance (RC delay) while minimizing the total area occupied by the signal line.
3Productivity
If the width of data lines or gate lines is reduced to improve transmittance, then the charging rate margin is improved, but the resistance of these lines increases
Solution Approach 1:
The data lines and gate lines are divided into multiple sections with varying widths. Critical sections where charging rate is most important are made narrower to improve transmittance, while sections requiring higher current drive are made wider to compensate for resistance increases.
Solution Approach 2:
Different portions of data and gate lines are assigned different width characteristics based on their functional requirements. This local optimization allows the system to achieve improved charging rate margins in critical areas while managing overall resistance through strategic width variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the charging rate of pixels, reduces image defects, and allows for narrower data and gate lines, improving transmittance and reducing the bezel width of the display device by minimizing RC delay and parasitic capacitance.
Implementation Method 1
an RC (resistive-capacitive) delay of the clock signal may be generated due to parasitic capacitance between the clock signal lines or between the signal lines that are adjacent to the clock signal lines
Implementation Method 2
Reducing the resistance of a clock signal line in turn results in a reduction of parasitic capacitance between the clock signal lines
Data Source
AI summary
A display device including a substrate, a gate driver disposed on the substrate and including a plurality of stages, a clock signal line disposed on the substrate, and transmitting a clock signal to at least one of the stages, a transistor disposed on the substrate, and a light blocking layer disposed between the substrate and the transistor and overlapping the transistor. The clock signal line includes a first conductive line and a second conductive line overlapping the first conductive line, and the first conductive line is disposed in the same layer as the light blocking layer.