Clock Signal Conditioning for Low-Power LSI Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for reducing power consumption in large-scale integrated circuits through clock signal conditioning either result in equal power dissipation in both slow and fast modes or lead to positive and negative bias temperature instability degradation.
Innovation Solution
A clock signal distribution system that produces a first clock signal with dual on-pulses of differing durations, achieving approximately 50% on-time and 50% off-time, with a 'dummy' on-pulse inserted and removed to reduce power dissipation and instability degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the off pulse of the clock signal is stretched to reduce frequency in slow mode, then power dissipation is reduced, but PBTI and NBTI degradation occurs due to unequal bias conditions
Solution Approach 1:
The patent changes the duty cycle parameter of the clock signal to approximately 50% in slow mode by inserting a dummy on-pulse, transforming the bias conditions experienced by gates from highly asymmetric (1/10 on-time, 9/10 off-time) to balanced (approximately equal on and off times), thereby reducing PBTI and NBTI degradation while maintaining low power dissipation
Solution Approach 2:
The patent introduces a dummy on-pulse as an intermediary element that temporarily balances the clock signal duty cycle during distribution, allowing the clock signal to experience equal on and off times throughout the distribution tree, which mitigates the harmful asymmetric bias conditions that cause PBTI and NBTI degradation
2Loss of energy
If clock gating is applied at the source to reduce power dissipation, then distribution circuit power is reduced, but PBTI and NBTI degradation results from unequal bias conditions
Solution Approach 1:
The patent modifies the clock signal parameter (duty cycle) to approximately 50% by inserting a dummy on-pulse, ensuring that all gates in the distribution circuit experience equal on and off times, thereby eliminating the PBTI and NBTI degradation caused by highly asymmetric bias conditions while maintaining reduced power dissipation
3Speed
If high frequency clock signal is carried through the distribution tree, then fast mode operation is enabled, but power dissipation remains high in slow mode
Solution Approach 1:
The patent uses periodic insertion of a dummy on-pulse into the clock signal during slow mode operation, creating a modified periodic waveform with approximately 50% duty cycle that allows the distribution tree to operate at low frequency with balanced bias conditions, thereby reducing power dissipation while maintaining proper logic operation
Solution Approach 2:
The patent dynamically changes the clock signal frequency and duty cycle parameters based on operating mode: in fast mode, high frequency with normal duty cycle is used for maximum speed; in slow mode, low frequency with approximately 50% duty cycle (achieved by dummy on-pulse insertion) is used to reduce power dissipation while maintaining reliability
Data Source
AI summary
Methods and apparatus for distributing clock signals to an integrated circuit provide for: producing, in a slow mode of operation, a first clock signal having at least first and second on-pulses of differing first and second on-times each period, respectively, where a sum of the first and second on-times is approximately equal to a sum of off-times each period; distributing the first clock signal through a distribution tree and terminating at a plurality of final buffer circuits that produce respective distributed clock signals from which respective second clock signals are produced to supply at least a portion of the integrated circuit; deleting the second on-pulse from each of the distributed clock signals each period to produce the respective second clock signals, the second clock signals each including at least a portion of the first on-pulse, but none of the second on-pulse each period.