Clock Signal Data Encoding via Pulse Width Modulation
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Solution Overview
Problem
Clock signals experience skew when transmitted across physical distances, affecting synchronization in systems, and existing methods for synchronization, such as PPS and IRIG time codes, have limitations in accurately transmitting time information over communication systems.
Innovation Solution
A method and circuit for encoding data transmission within a clock signal by varying the second edge of the clock cycle, using pulse width modulation to encode logical zeros and ones, allowing for synchronization and data transmission on a single line, enabling synchronization of systems and embedding virtual references within the main clock reference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is transmitted across physical distances for synchronization, then system synchronization is achieved, but skew is introduced into the clock signal
Solution Approach 1:
The patent combines synchronization function and data transmission function into a single clock signal channel. By merging these two functions, the system achieves both accurate synchronization and data communication without requiring separate transmission paths, thereby addressing the skew issue while maintaining synchronization accuracy.
Solution Approach 2:
The clock signal is designed to serve multiple purposes: it provides both the synchronization reference and carries data information through pulse width modulation. This multi-functionality allows the single signal to handle both timing reference and information transfer, resolving the contradiction between maintaining synchronization accuracy and transmitting data over the same medium.
2Reliability
If traditional separate signals are used for synchronization and data transmission, then synchronization accuracy is maintained, but system complexity increases
Solution Approach 1:
The invention merges the synchronization signal and data transmission signal into a single clock signal. This consolidation reduces the number of separate signals and components needed, thereby reducing system complexity while maintaining synchronization accuracy through the constant frequency reference.
Solution Approach 2:
The clock signal is designed as a universal signal that performs both synchronization and data transmission functions. This multi-functionality eliminates the need for separate dedicated synchronization and data channels, simplifying the overall system architecture while preserving the reliability of synchronization.
3Productivity
If pulse width modulation is used to encode data within the clock signal, then data transmission is achieved on a single line, but the duty cycle must be varied which may affect signal characteristics
Solution Approach 1:
The patent applies local quality by varying only the pulse width (local characteristic) of the clock signal while maintaining the overall frequency and timing structure intact. This allows data encoding through duty cycle variation without fundamentally altering the signal's synchronization properties, thus achieving data transmission while preserving signal stability.
Solution Approach 2:
The system dynamically adjusts the pulse width of the clock signal to encode data bits. This dynamic variation in duty cycle allows flexible data transmission while the underlying clock frequency remains stable, enabling adaptive data encoding without compromising the fundamental synchronization function.
Data Source
AI summary
A method of operating a clock circuit can include transmitting a clock signal from a transmitter of a first system to a receiver of a second system, where a first repeating edge of a clock cycle of the clock signal repeats at a predetermined constant frequency within the clock signal to synchronize operations of the second system, and varying, by the first system, a second edge within the clock cycle of the clock signal to transmit a data transmission within the clock signal.