Clock Signal Realignment for Multi-Clock Circuit Emulation
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Solution Overview
Problem
Existing circuit emulation processes are hindered by clock signals with varying frequencies, leading to inefficient emulation due to multi-cycle paths and throughput issues, particularly when derived or divided clock signals are used, affecting the performance and accuracy of emulation.
Innovation Solution
The method involves aligning the rising and falling edges of slower clock signals with those of faster clock signals within a circuit design, ensuring that multi-cycle paths are recognized and utilized during emulation, thereby optimizing the emulation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If clock signals with varying frequencies are used in circuit emulation, then the emulation can handle diverse clock domains and derived clock signals, but the emulation efficiency decreases due to multi-cycle paths and throughput issues
Solution Approach 1:
The patent changes the frequency parameter of slower clock signals to match the faster clock signal frequency. By realigning the frequency of the second clock signal (and other slower signals) to match the first clock signal (the fastest signal), the system eliminates multi-cycle paths and throughput issues while maintaining the ability to handle diverse clock domains. This parameter transformation resolves the contradiction between adaptability and productivity.
2Use of energy by moving object
If slower clock signals are used in the circuit design, then the circuit can operate at lower frequencies for power savings, but the emulation time increases due to frequency mismatches
Solution Approach 1:
The patent transforms the frequency parameter of slower clock signals to match the faster clock signal frequency during emulation. This allows the emulation to proceed at the higher frequency of the first clock signal, significantly reducing emulation time while the original design can still operate at lower frequencies for power savings when not being emulated.
3Adaptability or versatility
If derived clock signals are generated by combining multiple clock signals, then the circuit design flexibility increases, but the emulation performance deteriorates due to frequency ratio complications
Solution Approach 1:
The patent changes the frequency parameter of derived clock signals to match the fastest clock signal frequency, eliminating the frequency ratio complications that arise when combining multiple clock signals. This allows the emulation to maintain the design flexibility of using derived clock signals while achieving optimal emulation performance without throughput issues.
Data Source
AI summary
Circuit designs are emulated to verify the functionality of the circuit design. Emulating the circuit design includes obtaining a circuit design. The circuit design includes clock signals. Each of the clock signals is a data path clock signal. Further, a first clock signal of the clock signals is determined to be faster than a second clock signal of the clock signals. Rising edges and falling edges of the second clock signal are aligned with rising edges of the first clock signal to generate a realigned clock signal based on determining that the first clock signal is faster than the second clock signal. The circuit design is emulated using the realigned clock signal.