Clock Signal Remodeling for Faster Multicycle Path Prediction
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Solution Overview
Problem
Conventional clock signal prediction methods in circuit design emulation fail to leverage the multicycle properties of slower gated clock signals, leading to performance bottlenecks and inefficient emulation and prototyping processes.
Innovation Solution
Remodel the circuit design to align the rising and falling edges of slower clock signals with those of a faster root clock signal, enabling multicycle path prediction and improving emulation speed and compile times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional prediction methods use the root clock signal to predict gated clock signals, then hold time violations are prevented, but emulation performance is bottlenecked by the slower gated clock signal frequency
Solution Approach 1:
The patent introduces a remodeled second clock signal as an intermediary between the first clock signal and the circuit elements. This remodeled signal maintains the multicycle timing relationships required for reliable operation while being synchronized to the faster first clock signal, thereby enabling faster emulation without violating hold times
Solution Approach 2:
The patent changes the timing parameters of the second clock signal by remodeling it to align with the first clock signal's rising edges. This parameter transformation allows the circuit to operate at the higher frequency of the first clock signal while preserving the functional timing characteristics of the original slower clock signal
2Stability of the object's composition
If the data path operates at the slower gated clock signal frequency, then multicycle properties are preserved, but emulation and prototyping become performance bottlenecks
Solution Approach 1:
The patent creates a remodeled version of the second clock signal that copies its essential timing characteristics (rising and falling edges aligned with first clock signal rising edges) while operating at the faster frequency. This copy enables the data path to operate faster while maintaining the required multicycle timing properties
3Device complexity
If predicted enable logic is triggered by the root clock signal, then clock signal prediction is simplified, but the data path cannot utilize the slower gated clock signal effectively
Solution Approach 1:
The patent dynamically adjusts the clock signal relationships by remodeling the second clock signal to be triggered by the first clock signal's rising edges while maintaining its slower effective frequency for the data path. This dynamic remodeling allows the system to adapt timing relationships to maximize performance without increasing prediction logic complexity
Data Source
AI summary
Emulating a circuit design includes remodeling the clock signals of the circuit design. A circuit design includes clock signals that are based on a root clock signal. The clock signals are analyzed to identify a first clock signal of the clock signals that is faster than a second clock signal of the clock signals. The second clock signal is remodeled based on the first clock signal. An updated circuit design is generated based on remodeled second clock signal, and operation of the updated circuit design is emulated.