Clock Signal Routing Symmetry for Display Panel Defect Reduction
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Solution Overview
Problem
Active matrix flat panel displays experience optical deficiencies such as horizontal line defects due to load differences generated by clock signals in signal transmitting lines, necessitating a solution to reduce these issues.
Innovation Solution
The display device incorporates a substrate with gate and data lines, intersecting clock signal transmitting lines that change direction by approximately ninety degrees in specific regions, ensuring symmetry and uniformity in line lengths and widths, and includes a gate driver connected to these lines to minimize load differences and optical defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are transmitted through signal transmitting lines on the display panel, then the gate driver can generate gate signals, but load differences are generated causing optical deficiencies such as horizontal line defects
Solution Approach 1:
The patent applies asymmetry by intentionally designing the clock signal transmitting lines to have different directions in the first and second regions, creating a symmetric overall configuration that balances the signal transmission paths. This asymmetric local design leads to symmetric global characteristics that reduce load differences and optical deficiencies
Solution Approach 2:
The patent changes the dimensionality of the clock signal transmitting lines by introducing directional changes of approximately ninety degrees between the first and second regions. This dimensional transformation creates a more balanced signal distribution and reduces the harmful load differences that cause optical deficiencies
2Manufacturing precision
If the clock signal transmitting lines change direction by approximately ninety degrees in specific regions, then signal deviation is reduced, but the line configuration becomes more complex
Solution Approach 1:
The patent segments the clock signal transmitting lines into distinct first and second regions with different directional characteristics. This segmentation allows each region to be optimized independently for signal transmission, reducing overall signal deviation while maintaining manageable complexity through modular design
Solution Approach 2:
The patent changes the directional parameter of the clock signal transmitting lines by introducing approximately ninety-degree angle changes between regions. This parameter transformation optimizes signal transmission uniformity while the changes are implemented in a controlled manner to minimize increases in configuration complexity
Data Source
AI summary
A display device according to an exemplary embodiment of the present invention includes: a substrate, a plurality of gate lines formed on the substrate, a plurality of data lines formed on the substrate, a plurality of switching elements connected to the gate lines and the data lines, a plurality of clock signal transmitting lines formed on the substrate, and a gate driver connected to the gate lines and the clock signal transmitting lines. A direction of each of the clock signal transmitting lines is changed approximately ninety degrees in a first region and a second region. The regions are disposed between an edge of the substrate and the gate driver. A symmetry is present between portions of the clock signal transmitting lines arranged in the first region and the second region.