Clock-Signal Comparator for Real-Time Skew Detection
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Solution Overview
Problem
Current data processing systems face challenges in managing clock skew between different clock domains, particularly in generating clocks with integer frequency divisions while maintaining low skew, and existing static timing analysis tools are inadequate for detecting clock skew in external clock paths.
Innovation Solution
An integrated circuit with a clock-signal comparator that dynamically checks for correspondence between clock edges within a predetermined time window, enabling reliable detection and control of clock skew, even in dynamic operating conditions and across different clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If static timing analysis tools are used to check clock skew, then analysis can be performed on circuit portions, but external clock paths involving board-level components cannot be analyzed
Solution Approach 1:
The patent introduces a clock skew detector circuit as an intermediary component that bridges the gap between internal circuit analysis and external clock path monitoring. This detector is placed within the integrated circuit but monitors clock signals from external sources, enabling analysis of board-level clock paths that static timing tools cannot access.
Solution Approach 2:
The system performs self-diagnosis by incorporating a clock skew detector that automatically monitors and detects clock skew conditions in real-time during circuit operation, eliminating the need for external analysis tools and providing continuous verification of clock signal integrity.
2Manufacturing precision
If explicit placement of circuit elements is used to reduce clock skew, then fine-tuning of circuit design is achieved, but the methodology is error-prone and not easily transferable to different device sizes and structures
Solution Approach 1:
The clock skew detector provides real-time feedback about actual clock skew conditions in the operating circuit. This feedback mechanism allows the system to automatically identify skew problems without requiring complex manual placement and tuning of circuit elements, reducing design complexity while maintaining precision.
Solution Approach 2:
Instead of changing the physical placement of circuit elements to control clock skew, the patent changes the monitoring approach by detecting clock skew through signal analysis. This parameter change from physical layout adjustment to signal-level detection simplifies the design process and makes it adaptable to different device sizes and structures.
3Manufacturing precision
If PLL clock generators are used to control clock skew, then relative timings of clock edges can be modified, but this approach does not work for externally generated clock signals
Solution Approach 1:
The clock skew detector acts as an intermediary monitoring device that observes externally generated clock signals without requiring modification of the external clock generation architecture. It detects timing differences between clock domains while the external PLLs continue to operate independently, providing timing control capability for externally generated clocks.
Data Source
AI summary
A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving respective further clock signal. Checking logic is provided within the clock signal comparator to check for a correspondence between the clock edge of the reference clock signal and a corresponding clock edge of the further clock signal within a predetermined time window. The checking logic is operable to check for the correspondence during operation of the data processing system. The clock-signal comparator can be provided on an integrated circuit or as part of the data processing apparatus having at least two different timing domains such as timing domains associated with two different instances of the same clock. Furthermore the clock-signal comparator is implemented in a hardware description language and integrated in a simulation of the operation of a data processing apparatus to detect timing errors that arise from numerical artifacts of the simulation as well as timing errors that arise from configuration and layout of the circuit elements of the data processing apparatus being simulated.