Clock Signal Stop Detection Circuit for Semiconductor Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor technologies face difficulties in detecting clock signal abnormalities when only one clock signal source is present, as they require multiple sources to monitor and detect faults effectively.
Innovation Solution
A semiconductor device with a clock signal stop detection circuit that detects the edge of input data and resets count values using both the clock signal and its inverted signal to identify abnormality, allowing for fault detection in a single system by using a clock signal stop detection cell integrated into the data retention circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock signal sources are used for monitoring, then clock signal abnormality detection capability is improved, but device complexity increases
Solution Approach 1:
The single clock signal source performs self-monitoring by feeding back to the monitoring device, allowing the system to detect its own abnormalities without requiring additional independent clock sources. The clock signal source monitors itself through the counting mechanism that detects stoppages or abnormalities.
Solution Approach 2:
The single clock signal source serves dual functions: both as the operational clock signal for the semiconductor device and as the monitoring signal for detecting abnormalities. This multi-functionality eliminates the need for separate monitoring clock sources.
2Device complexity
If a single clock signal source is used, then device complexity is reduced, but clock signal abnormality detection capability deteriorates
Solution Approach 1:
The clock signal source feeds back its signal to the monitoring device, creating a closed-loop system where the operational clock signal is simultaneously used for monitoring. This feedback mechanism enables the detection of abnormalities in the single clock source without requiring additional hardware.
Solution Approach 2:
The monitoring device acts as an intermediary that intercepts the clock signal from the single clock source and analyzes it for abnormalities. This intermediary function allows the system to monitor the clock signal without requiring a separate clock source.
3Measurement precision
If multiple counters are used for monitoring different clock sources, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The single counter performs multiple functions by counting both the operational clock signal and the monitoring clock signal sequentially or concurrently, eliminating the need for separate counters for each clock source while maintaining detection precision.
Solution Approach 2:
The monitoring function and operational function are merged into a single counter device that handles both the primary clock signal counting and the monitoring clock signal counting, reducing hardware complexity while preserving measurement capabilities.
Data Source
AI summary
A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.