Clock Signal Test Circuit Multiplexing for Display Panel Layout
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Solution Overview
Problem
The existing technologies for testing gate drive circuits require a large number of clock signal channels, which is inefficient and costly, and occupies significant peripheral layout space, making it difficult to meet the demand for signal channels and optimize the utilization of glass area in display panels.
Innovation Solution
A clock signal test circuit with a reduced number of clock signal channels is implemented, utilizing N clock control signal lines and M control sub-circuits with pull-down branches to function as a larger number of clock signal channels, achieving the equivalent functionality of 30 clock signals using only 13 channels, thereby reducing the number of clock signal channels needed and optimizing the layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large number of clock signal channels are used for testing gate drive circuits, then the testing functionality is complete and reliable, but the peripheral layout space is significantly occupied and the cost increases
Solution Approach 1:
The patent applies multi-functionality by enabling a single clock signal channel to perform multiple testing functions. The test circuit uses multiplexing techniques where one clock signal channel can sequentially or simultaneously control multiple control sub-circuits to test different gate drive circuit functions, thereby reducing the total number of clock signal channels needed while maintaining complete testing coverage
Solution Approach 2:
The patent combines multiple testing functions into a unified test circuit architecture. By merging the control logic and signal routing, the system allows a reduced set of clock signal channels to control multiple control sub-circuits that collectively perform the same testing functions as would require more separate channels, thus optimizing peripheral layout space
2Reliability
If a large number of clock signal channels are used for testing gate drive circuits, then the testing coverage is comprehensive, but the test device cost increases
Solution Approach 1:
The test device implements multi-functionality by designing a clock signal channel that can be dynamically allocated to control multiple control sub-circuits. This allows comprehensive testing coverage to be achieved with fewer physical channels, directly reducing the cost of the test device while maintaining the ability to test all necessary gate drive circuit functions
Solution Approach 2:
The patent changes the operational parameters of the clock signal channels by implementing dynamic timing and control logic. The same clock signal channel can be reassigned to different control sub-circuits at different time intervals or under different control conditions, allowing comprehensive testing coverage with reduced channel count, thereby lowering test device cost
3Productivity
If N clock control signal lines are used to control multiple control sub-circuits, then the number of clock signal channels is reduced, but the control logic complexity increases
Solution Approach 1:
The patent segments the control logic into modular control sub-circuits, each responsible for specific testing functions. This segmentation allows the control logic to be organized in a structured manner, making it easier to manage and implement despite the increased complexity of controlling multiple sub-circuits with fewer clock signal channels
Solution Approach 2:
The patent introduces intermediary control logic and signal routing mechanisms that mediate between the reduced set of clock signal channels and the multiple control sub-circuits. These intermediaries manage the complexity by providing standardized interfaces and control protocols, allowing efficient channel utilization while keeping the control logic organized and manageable
Data Source
AI summary
The present application discloses a clock signal test circuit, a control method thereof, a display panel and a test device. The clock signal test circuit comprises: N clock control signal lines; M control sub-circuits, each of which includes at least two control branches, wherein each of the control branches is configured to output a signal input from the input signal line to the corresponding output signal line under the control of a signal input from the corresponding clock control signal line; and a pull-down sub-circuit including N pull-down branches, wherein each of the pull-down branches is configured to output the first power supply voltage to the corresponding output signal line under the control of the signal input from the corresponding clock control signal line.