Clock Skew-Adjustable Chip Clock Architecture for Programmable Logic
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Solution Overview
Problem
The existing fishbone-type clock architecture in programmable logic chips suffers from significant clock skew, which worsens with increasing chip size, hindering performance, and existing ASIC clock tree synthesis technologies cannot be integrated with programmable logic units due to differences in layout, blocking, and wiring, making it difficult to optimize clock skew in these chips.
Innovation Solution
A clock skew-adjustable chip clock architecture is introduced, featuring a global clock and regional clocks with delay adjustment cells that have parallel delay paths with different delay values, allowing for configuration-based gating to achieve target delays and adjust clock skew modes, including zero-skew, lead skew, and lag skew modes, to accommodate varying application scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If fishbone-type clock architecture is used, then hierarchical clock design is achieved, but clock skew becomes large
Solution Approach 1:
The clock tree is segmented into multiple independent regional clocks, each serving a specific chip region. This segmentation allows localized delay adjustment without affecting the entire clock tree, enabling precise clock skew control while maintaining hierarchical structure
Solution Approach 2:
Delay adjustment cells are introduced to change the temporal parameters of clock signals in each region. By varying delay values in parallel delay paths, the system can compensate for path length differences and achieve minimal clock skew across different regions
2Quantity of substance
If chip size increases, then programmable resources increase, but clock skew increases
Solution Approach 1:
The chip is divided into multiple regions, each with its own regional clock and delay adjustment cell. This segmentation isolates delay issues to local regions, allowing the system to scale chip size while maintaining acceptable clock skew through localized compensation
Solution Approach 2:
The delay adjustment cells receive configuration signals that enable them to compensate for delay variations. This feedback mechanism allows the system to adapt to changing clock skew conditions as chip size increases, maintaining timing precision across larger devices
3Manufacturing precision
If ASIC clock tree synthesis technology is applied, then clock skew is reduced, but integration with programmable logic units becomes difficult
Solution Approach 1:
The clock architecture is designed with universal delay adjustment cells that can be integrated with both ASIC clock tree synthesis and programmable logic units. These cells serve multiple functions: compensating for ASIC-style clock trees while also accommodating the flexible configuration needs of programmable logic, thereby achieving both low clock skew and high adaptability
Data Source
AI summary
A delay adjustment cell is disposed in a channel of at least one regional clock of a chip clock architecture, and the delay adjustment cell includes a plurality of parallel delay paths with different delay values. The delay adjustment cell gates one of the delay paths based on an obtained configuration signal such that a connected regional clock has a corresponding target delay, and a target delay of each regional clock corresponds to a clock skew mode of the programmable logic chip. A clock skew between different regional clocks is adjusted by controlling the gated delay path in the delay adjustment cell, such that a clock skew of the chip can be adjusted in a relatively large range. Under the same resource configuration, different path choices of the delay adjustment cell lead to different clock skews to meet different clock skew modes in different application scenarios.