Clock Generation for Multiple Domains Using Skew Adjustment
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Solution Overview
Problem
Integrated circuits with multiple clock domains face challenges in data exchange due to clock edge misalignment and metastability issues, particularly when operating at different frequencies, leading to reduced transfer rates and increased design complexity.
Innovation Solution
A system that uses a differential clock distribution and programmable clock dividers to align clock edges across domains, along with clock pulse suppression techniques, allowing for efficient data transfer between clock domains with different frequencies without the need for large data buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate PLLs are used for each clock domain to operate at different frequencies, then each domain can run independently at optimized speeds, but clock edge misalignment occurs between domains
Solution Approach 1:
The system segments the clock distribution into hierarchical levels: a common reference clock feeds multiple PLLs, each PLL generates clocks for specific domains. This segmentation allows independent frequency optimization per domain while maintaining a unified reference point for synchronization.
Solution Approach 2:
A skew adjust circuit acts as an intermediary between PLLs to synchronize clock edges. The circuit introduces adjustable delays to align clock edges from different PLLs, serving as a mediator that reconciles the timing differences caused by separate clock generation paths.
2Reliability
If data buffers are increased to accommodate clock frequency mismatch, then data transfer reliability improves, but device complexity and resource usage increase
Solution Approach 1:
The system performs preliminary synchronization by aligning clock edges using skew adjustment circuits before data transfer occurs. By pre-synchronizing the clock domains, the system eliminates the need for large buffers that would otherwise be required to handle timing mismatches, thereby maintaining reliability while reducing complexity.
3Manufacturing precision
If skew adjust circuits are added to synchronize PLLs, then clock edge alignment improves, but device complexity increases
Solution Approach 1:
The skew adjustment functionality is merged with the existing PLL infrastructure rather than being implemented as completely separate synchronization circuits. The skew adjust circuits are integrated into the clock distribution network, sharing resources with the PLLs they synchronize, thereby reducing overall device complexity.
4Adaptability or versatility
If clock domains are increased to improve functionality, then system versatility improves, but design overhead increases
Solution Approach 1:
The clock distribution system is designed with universal components that can serve multiple domains. The common reference clock and standardized PLL modules can be configured to support different frequencies and domain requirements, allowing the same infrastructure to accommodate varying system functionalities without proportionally increasing design overhead.
Data Source
AI summary
This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated by a central clock to an appropriate frequency. By using embodiments of the invention, clock crossing circuitry between domains need not run at the highest clock frequency of the entire circuit, but rather the clock crossing circuitry need only operate at the highest frequency of the two domains sharing data.