Clock Skew Compensation in Audio Buffers

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Solution Overview

Problem

In packet switched networks, clock frequency differences between sending and receiving communicating devices cause buffer overruns and underruns due to clock skew, leading to packet slips and synchronization errors, which existing methods struggle to fully address, especially in scenarios where synchronization is not possible or practical.

Innovation Solution

A method and arrangement in a receiving communicating device that continuously estimates and compensates for clock skew by adjusting the number of audio samples read from a buffer, using interpolation to resample and synchronize with the sending device's clock frequency, potentially eliminating the need for a separate de-jittering buffer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a de-jittering buffer is used to compensate for delay jitter, then buffer underrun is avoided, but overall delay is increased

Engineering Contradiction:
Improvebuffer underrun avoidanceVSAvoidoverall delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the de-jittering buffer function with the clock skew compensation buffer into a single unified buffer structure. This combined buffer handles both delay jitter variation and clock skew accumulation simultaneously, avoiding the need for separate buffers and reducing total buffer memory requirements while maintaining reliability and minimizing delay.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified buffer serves multiple functions: it compensates for delay jitter by adjusting playback timing, compensates for clock skew by accumulating time differences, and prevents both buffer underrun and overrun conditions. This multi-functional approach replaces what would traditionally require separate dedicated buffers for each compensation mechanism.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Device complexity

If clock skew is not compensated, then device complexity is reduced, but packet slips and synchronization errors increase

Engineering Contradiction:
Improvecompensation mechanismVSAvoidsynchronization accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements feedback by continuously monitoring the actual packet arrival times and comparing them against expected arrival times based on the nominal clock frequency. The accumulated time difference (clock skew) is fed back to adjust the number of samples read from the buffer, creating a closed-loop system that automatically compensates for frequency differences without complex external synchronization infrastructure.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system dynamically changes the playback parameter (number of samples read per packet) based on the measured clock skew. Instead of requiring exact frequency matching between transmitter and receiver, the invention adapts the sample count parameter to compensate for frequency drift, allowing reliable operation with simple quarter-crystal oscillators.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the buffer size is increased to accommodate clock skew variations, then packet slips are reduced, but memory usage increases

Engineering Contradiction:
Improvepacket slip preventionVSAvoidbuffer memory
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent employs dynamic buffer management where the effective buffer utilization varies based on the measured clock skew. The system calculates the optimal number of samples to read from the buffer based on accumulated time differences, allowing the buffer to adapt its consumption rate dynamically. This prevents the need for a permanently oversized buffer while maintaining protection against packet slips under varying clock conditions.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces packet slips and synchronization errors by synchronizing the sample rate, minimizing buffer overflows and underflows, and can operate without a separate de-jittering buffer, thereby improving audio playback quality and reducing delays.

Implementation Method 1

an interpolating unit, arranged to resample the N samples from the buffer to M samples by interpolation

Methodology Applied
Scientific EffectInterpolation:

Data Source

PatentUS7949015B2Clock skew compensation
Publication Date: 2011.05.24 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US7949015B2 patent drawing
  • US7949015B2 patent drawing
  • US7949015B2 patent drawing

AI summary

A method and arrangement in a receiving communication device for compensating for the difference between the clock-frequency controlled sample rate of the receiving device and the sample rate of a sending communication device. The sending device transmits packets comprising M audio samples to be stored in a buffer in the receiving device accommodating at least 2·M samples before play-out. An estimation of the clock skew is continuously updated from a calculated accumulated difference between an expected and an actual point of time of reception of the M audio samples. Before play-out, an adjusted number N of audio samples to be read from the buffer before play-out is calculated using the estimated clock skew. Thereafter, the N audio samples are resampled by interpolation to M audio samples to play-out.