Clock Recovery Circuit Skew Calibration Using Multi-Level Detection
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Solution Overview
Problem
In electronic devices, accurately recovering clock signals is challenging due to increased communication speed and decreased circuit size, especially when multiple communication lines and clock signals are involved, leading to difficulties in maintaining uniform skew between clock signals.
Innovation Solution
An electronic circuit with a data recovery circuit and a clock recovery circuit that adjusts skew between clock signals by comparing signal levels with reference levels, adjusting delays based on error signs and transitions, and calibrating skew between clock signals to ensure accurate timing and reliable data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If communication speed is increased and circuit size is decreased, then communication efficiency is improved, but clock signal recovery accuracy deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the recovered data signal is fed back to the clock recovery circuit. The clock recovery circuit uses this feedback data along with multiple reference levels to continuously adjust and refine the clock signal timing, compensating for skew caused by high-speed communication and small circuit dimensions.
Solution Approach 2:
The patent changes the parameter of reference level quantity from the conventional single reference level to multiple reference levels (at least three: first higher than mid-level, second equal to mid-level, third lower than mid-level). This parameter change enables more precise detection of data transitions and better compensation for timing skew in high-speed communication scenarios.
2Adaptability or versatility
If multiple communication lines and clock signals are employed, then data exchange capability is improved, but skew control between clock signals deteriorates
Solution Approach 1:
The patent segments the clock recovery function into multiple independent clock recovery circuits, each responsible for recovering a specific clock signal from its corresponding communication line. Each circuit independently processes its data signal and adjusts its clock signal timing, enabling parallel operation of multiple communication lines while maintaining individual skew control for each clock signal.
Solution Approach 2:
The patent applies local quality by giving each clock recovery circuit its own set of reference levels and comparison circuits tailored to its specific communication line characteristics. This localized approach allows each circuit to optimize its clock recovery independently, compensating for line-specific skew while maintaining overall system versatility.
Data Source
AI summary
A data recovery circuit adjusts skew between a first and second clock signals when a signal level of recovered data changes relative to first reference level between a first timing of the first clock signal and a second timing of the second clock signal. Prior to adjusting the skew, a first signal level of the recovered data at the first timing is compared to a second and/or a third reference level. A second signal level at the second timing is compared to the second and/or the third reference level. The skew is adjusted based on a first sign of an error of the first signal level relative to one of the second and third reference levels. The first sign is opposite to a second sign of an error of the second signal level relative to another one of the second and third reference levels.