Multiphase Clock Skew Calibration Circuit With Comparator-Based Correction
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Solution Overview
Problem
Conventional clock skew calibration circuits in high-speed semiconductor circuits suffer from residual skew errors due to amplifier offset and noise, leading to high-frequency jitter and power consumption issues, necessitating a low-power, accurate solution for detecting and correcting clock skew.
Innovation Solution
An electronic circuit comprising a filtering circuit to generate a differential voltage representing clock skew, a discrete time integrator to amplify this voltage, a comparator to determine divergence, and a clock-skew corrector to modify clock edges, thereby reducing skew between multi-phase clock signals with low power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional amplifier-based skew calibration circuits are used, then skew detection capability is provided, but amplifier offset and noise introduce residual skew errors and consume excessive power
Solution Approach 1:
The patent extracts and eliminates the amplifier component from the skew calibration circuit, replacing it with a direct comparator-based architecture. This removal of the amplifier (the harmful element) eliminates the source of offset and noise while reducing power consumption, directly resolving the contradiction between measurement precision and energy use.
Solution Approach 2:
The patent employs a simple comparator circuit instead of a complex amplifier, using a less sophisticated but sufficiently functional component that consumes less power and introduces fewer errors. This substitution of a simpler component achieves the required skew detection without the drawbacks of the amplifier.
2Ease of operation
If amplifier-based skew calibration circuits are used, then skew detection is enabled, but offset errors limit residual skew performance
Solution Approach 1:
The patent removes the amplifier from the circuit architecture, eliminating the offset error source. The comparator directly compares clock phases without the intermediate amplification stage that introduces offset, thereby maintaining calibration capability while improving residual skew performance.
Solution Approach 2:
The patent introduces a differential voltage representation as an intermediary that directly captures skew information without amplification. This differential voltage serves as a clean mediator between the clock signals and the comparator, preserving skew measurement accuracy without amplifier-induced offset errors.
3Measurement precision
If multiple stages of amplification are used, then skew detection sensitivity is improved, but noise addition and power consumption increase
Solution Approach 1:
The patent extracts and removes the amplification stages entirely, replacing them with a direct comparator approach. This elimination of multiple amplification stages prevents the accumulation of noise while maintaining sufficient skew detection sensitivity through the differential voltage comparison method.
Solution Approach 2:
The patent converts the potentially harmful effect of needing high sensitivity into a benefit by using a differential voltage approach that naturally provides sensitivity without amplification. The differential configuration inherently rejects common-mode noise while maintaining sensitivity to differential skew signals.
Data Source
AI summary
The electronic circuit for multiphase clock skew calibration of at least one example embodiment provides a novel low power solution to detect clock skew errors with very high accuracy, of the order of a few femto seconds, and corrects clock skew errors and decreases and/or minimizes high frequency jitter in a data path of the electronic circuit.