Clock Skew Correction for Multi-Interface Server Modules
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Solution Overview
Problem
High-speed peripheral chips on server mainboards experience clock skew due to varying standards for determining synchronous clock signal levels, leading to time discrepancies between the clock signals transmitted to these chips and the CPU.
Innovation Solution
A method and system for correcting clock skew by determining delay parameters for modules, calculating and adjusting clock phases, and generating corrected clocks based on these parameters to synchronize clock signals across modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If various standards are used for determining synchronous clock signal levels in different high-speed peripheral chips, then compatibility with diverse chip interfaces is improved, but clock skew between chips and CPU occurs
Solution Approach 1:
The patent applies local quality by allowing different interface standards (LVCOMS, GTL, etc.) to have their own specific threshold levels for determining clock signal high/low states. Each interface type maintains its own characteristics while the system as a whole achieves synchronization through individualized delay parameter calculations for each module based on its specific interface requirements.
Solution Approach 2:
The patent changes parameters by calculating specific delay parameters for each module based on its interface characteristics and path length. The delay parameter is adjusted individually for each module to compensate for variations in interface standards, thereby achieving clock synchronization across diverse interfaces without requiring a unified interface standard.
2Reliability
If different threshold levels are used for different interface types, then interface-specific performance is improved, but time skew between modules increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating delay parameters for each module before actual clock signal transmission. The system determines the specific interface type and path length of each module in advance, calculates the required delay parameter accordingly, and uses this pre-calculated parameter to adjust the clock phase, thereby eliminating time skew before it occurs.
Solution Approach 2:
The patent uses copying by creating a reference model for delay calculation that accounts for different interface types. The delay parameter calculation methodology is copied and adapted for each specific interface type (LVCOMS, GTL, etc.), allowing the system to handle various interface standards while maintaining consistent synchronization through the unified delay parameter adjustment mechanism.
3Adaptability or versatility
If clock signals are transmitted to multiple modules with different interface standards, then system versatility is improved, but clock phase consistency deteriorates
Solution Approach 1:
The patent applies local quality by allowing each module to have its own specific delay parameter tailored to its interface type and path characteristics. Instead of forcing a uniform clock phase approach, the system adjusts each module's clock phase individually based on its local interface requirements, thereby maintaining both multi-interface versatility and clock phase consistency.
Solution Approach 2:
The patent applies dynamics by making the clock phase adjustment flexible and adaptive rather than fixed. The delay parameter is dynamically determined based on the specific interface type and path length of each module, allowing the system to adapt to different interface configurations while maintaining overall clock synchronization.
Data Source
AI summary
A clock skew correcting method, device and system are provided. The method includes: determining at least two modules; determining a period of a clock signal and calculating a delay parameter of each of the at least two modules, in a case where a clock generator transmits the clock signal to each of the at least two modules; determining one of the at least two modules as a slave module and the other of the at least two modules as at least one main module; correcting a clock phase for each of the at least one main module based on the delay parameter of the slave module; and performing, for each of the at least one main module, the following step of generating a corrected clock for the main module based on the period and the corrected clock phase for the main module.