Phase Interpolator Clock Skew Correction Using Intermediate Currents
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Solution Overview
Problem
Conventional phase interpolator circuits experience phase difference shifts between output clock signals due to skew mismatches, leading to reduced timing margins and hindered high-speed operations.
Innovation Solution
A phase interpolator circuit with a first and second generation circuit generating intermediate currents based on input clock signals, a synthesis circuit for combining these currents, and a correction circuit to adjust current amounts using correction codes to correct phase differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase interpolator circuits are used to generate output clock signals, then phase adjustment is achieved, but phase difference shifts occur due to skew mismatches leading to reduced timing margins
Solution Approach 1:
The patent implements a feedback mechanism where the phase difference between output clock signals is continuously monitored and measured. Based on this feedback, the control circuit adjusts the activation timing of switch elements to compensate for phase difference shifts, thereby maintaining accurate phase relationships and preserving timing margins for reliable high-speed operations
Solution Approach 2:
The patent dynamically changes the timing parameters of switch element activation based on detected phase difference shifts. By adjusting when switches are turned on and off in response to measured skew mismatches, the system corrects phase errors and maintains stable phase differences between output clock signals
2Adaptability or versatility
If phase interpolation is performed using conventional circuits, then clock phase adjustment is achieved, but skew mismatches cause phase difference shifts that hinder high-speed operations
Solution Approach 1:
The system uses real-time feedback from phase difference detection to dynamically adjust switch timing, enabling the phase interpolator to maintain accurate phase relationships even at high operating speeds where skew mismatches would otherwise cause failures
Solution Approach 2:
The patent introduces dynamic adjustment of switch element timing based on real-time phase difference measurements. This dynamic control allows the circuit to adapt to varying conditions and maintain stability at high speeds, transforming a static circuit into one that can respond to and correct for timing variations
Data Source
AI summary
A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.