Integrated Circuit Clock Distribution Network Skew Control
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Solution Overview
Problem
Unintentional clock skew in synchronous integrated circuits leads to performance and robustness issues due to varying arrival times of the clock signal at different sinks, increasing design margins and overhead costs.
Innovation Solution
The automatic synthesis of clock distribution networks with distributed, dynamic de-skew circuits that compare arrival times of clock signals using phase detectors and adjust variable delay buffers to minimize clock skew between neighboring partitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock distribution networks are used without dynamic de-skew circuits, then device complexity is reduced, but clock skew increases leading to performance degradation
Solution Approach 1:
The clock distribution network is divided into multiple partitions, each with its own local de-skew circuit. This segmentation allows independent optimization of each partition's clock skew without affecting the entire system, resolving the contradiction by distributing complexity locally while improving overall reliability.
Solution Approach 2:
The patent implements dynamic de-skew circuits that continuously adjust clock signal timing based on real-time phase detection. This dynamic adjustment capability enables the system to adapt to process variations and temperature changes, improving clock skew control reliability while the automation reduces the perceived complexity for designers.
2Reliability
If design margins are increased to account for clock skew, then reliability improves, but productivity decreases due to larger design overhead
Solution Approach 1:
The patent employs phase detectors that continuously monitor clock signal arrival times and provide feedback to de-skew circuits. This closed-loop feedback system automatically compensates for clock skew without requiring conservative design margins, thereby improving reliability while maintaining design efficiency and productivity.
Solution Approach 2:
The de-skew circuits are self-regulating systems that automatically adjust their own operation based on phase detector feedback. This self-service capability eliminates the need for external design margin adjustments, allowing the system to maintain high reliability without sacrificing productivity or requiring additional design overhead.
3Productivity
If clock frequency is increased to improve performance, then productivity increases, but clock skew becomes more significant worsening reliability
Solution Approach 1:
The dynamic de-skew circuits operate in real-time to continuously compensate for clock skew even at high frequencies. By making the de-skew mechanism dynamic rather than static, the system can maintain reliable clock synchronization across all operating frequencies, enabling productivity improvement without sacrificing reliability.
Solution Approach 2:
The patent adjusts timing parameters dynamically through variable delay buffers controlled by de-skew logic. This ability to change timing parameters in real-time allows the system to maintain optimal clock skew compensation across varying clock frequencies, supporting both high productivity and reliability simultaneously.
Data Source
AI summary
In one embodiment of the invention, a method for designing an integrated circuit is disclosed. The method includes automatically partitioning clock sinks of an integrated circuit design into a plurality of partitions; automatically synthesizing a clock tree from a master clock generator into the plurality of partitions to minimize local clock skew within each of the plurality of partitions; and automatically synthesizing clock de-skew circuitry into each of the plurality of partitions to control clock skew between neighboring partitions.