Clock Skew Compensation Circuit Using Median Delay Phase Selection
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Solution Overview
Problem
Clock skew occurs during the actual operation of a system due to changes in the surrounding environment, despite initial optimization during the training process, as the patterns of data input and output differ from those tested during training.
Innovation Solution
A method and circuit for compensating clock skew by generating (2M+1) delay clock signals and applying them to delay data, determining a dominant logic value and median delay time, and adjusting the clock signal phase using these values to minimize skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock is optimized during the training process, then clock skew is minimized during training, but clock skew occurs during actual operation of the system
Solution Approach 1:
The patent implements a dynamic clock skew compensation mechanism that continuously monitors and adjusts clock phase during system operation. The compensation circuit receives the input clock signal, generates multiple delayed clock signals, and dynamically selects the optimal phase based on real-time data sampling, allowing the system to adapt to environmental changes such as temperature variations that occur during actual operation.
Solution Approach 2:
The patent employs a feedback mechanism where the compensation circuit continuously samples data using multiple delayed clock signals, determines the optimal phase through comparison and selection logic, and adjusts the clock phase accordingly. This closed-loop feedback ensures that clock skew is compensated in real-time based on actual operating conditions, maintaining synchronization between clock and data throughout system operation.
2Reliability
If multiple delay clock signals are generated and applied to delay data, then real-time clock skew compensation is achieved, but device complexity increases
Solution Approach 1:
The patent segments the clock signal into multiple delayed versions, each with a different phase offset. By dividing the clock signal path into multiple parallel branches with controlled delays, the system can sample data at different phases independently and select the optimal one, achieving fine-grained clock skew compensation without requiring complex continuous adjustment mechanisms.
Solution Approach 2:
The patent generates (2M+1) delay clock signals, which is an excessive number compared to the minimum needed for basic compensation. This over-sampling approach ensures that the optimal clock phase can be found with high precision by comparing multiple candidates, trading increased circuit complexity for improved compensation accuracy and robustness against varying skew conditions.
Data Source
AI summary
A method of compensating clock skew may include generating (2M+1) detected values by applying (2M+1) delay clock signals to (2M+1) pieces of delay data, wherein M is a natural number, determining a dominant logic value based on a comparison of a number of logic high detected values and a number of logic low detected values from among the (2M+1) detected values, determining a median delay time based on a number of the (2M+1) detected values having the dominant logic value, and adjusting a phase of a clock signal using the median delay time.