Configurable Clock Skew Routing for Time-Borrowing Circuits
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Solution Overview
Problem
Conventional time borrowing schemes in integrated circuits face limitations in achieving optimal performance due to limited clock delays and complexity, often resulting in suboptimal timing and increased power consumption.
Innovation Solution
The implementation of a programmable integrated circuit with multiple clock distribution networks and adjustable delay circuitry allows for intelligent placement and routing of clock sources, enabling customizable clock skews to optimize circuit performance by borrowing time from fast logic paths to support slower paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional time borrowing schemes are used to address timing delays in slow logic paths, then clock frequency can be maintained, but the number of available clock delays is limited and device complexity increases
Solution Approach 1:
The clock distribution network is segmented into multiple independent clock trees, each serving different regions of the circuit. This allows different clock phases and delays to be provided to different logic paths without requiring a single complex global clock network, thereby maintaining high clock frequency while reducing overall network complexity.
Solution Approach 2:
The clock network incorporates dynamically adjustable delay elements that can be programmed to provide different clock skew values. This dynamic adjustability allows the system to optimize timing for different operating conditions without increasing structural complexity, as the same physical network can be reconfigured for different timing requirements.
2Manufacturing precision
If multiple clock sources are added to provide optimal clock delays for different regions, then timing performance improves, but power consumption increases
Solution Approach 1:
A single clock source is designed to perform multiple functions by generating multiple clock phases and distributing them through different clock trees. This multi-functional approach provides the timing accuracy benefits of multiple clock sources while avoiding the power consumption penalty of actually having multiple independent clock generation units.
Solution Approach 2:
Clock distribution buffers and delay elements serve as intermediaries between the single clock source and various logic regions. These intermediaries shape and time the clock signals locally, providing region-specific timing optimization without requiring additional clock sources, thus maintaining low power consumption while achieving high timing accuracy.
3Productivity
If clock skew is increased to borrow time from fast paths for slow paths, then circuit performance improves, but race conditions and clock timing issues may occur
Solution Approach 1:
Different clock skew values are applied locally to different regions of the circuit based on their specific timing requirements. Fast logic paths receive minimal or zero skew while slow paths receive appropriate positive skew. This localized approach maximizes circuit performance by enabling time borrowing where needed while maintaining clock timing reliability in regions where it is not required.
Solution Approach 2:
The clock network allows dynamic adjustment of clock skew parameters for different clock trees and regions. By programmably changing the skew parameter, the system can optimize for performance when timing allows or maintain conservative reliable timing when needed, thus balancing circuit performance and clock timing reliability through parameter optimization rather than structural changes.
Data Source
AI summary
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.