Clock Skew Analysis via Shared Path Delay Segmentation
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Solution Overview
Problem
As VLSI circuits shrink, the increasing ratio of routing delay to logic delay necessitates a more accurate clock skew analysis to ensure maximum frequency operation, but existing methods are either time and resource intensive or produce biased results due to static and dynamic delay variations from process, voltage, and temperature differences.
Innovation Solution
Generating and storing sets of delay values for paths from a clock source through a clock tree to nodes in an integrated circuit, including maximum and minimum delay values, and common delay values for shared paths, to accurately determine clock skew without unduly impacting computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If maximum and minimum delay values are used for accurate clock skew analysis, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The clock tree is segmented into shared portions and unique portions. Delay values are calculated separately for shared paths (common delay) and unique paths (individual delay). This segmentation allows accurate clock skew analysis by focusing computational resources only on the unique delay variations while accounting for shared path delays once, thereby reducing overall computational complexity while maintaining precision.
2Measurement precision
If static and dynamic delay variations are accounted for, then measurement precision is improved, but loss of time increases
Solution Approach 1:
Delay values for shared portions of the clock tree are pre-calculated and stored as common delay values before performing clock skew analysis. When analyzing clock skew between two nodes, these pre-calculated common delays are retrieved and subtracted from the total delay differences, leaving only the unique path delay variations to be analyzed. This preliminary action significantly reduces analysis time while maintaining accuracy by accounting for both static and dynamic delay variations.
3Reliability
If worst-case clock skew calculations are performed, then reliability is improved, but measurement precision deteriorates due to bias
Solution Approach 1:
The patent applies different quality requirements to different portions of the clock tree. Shared portions are analyzed once to determine common delay characteristics, while unique portions are analyzed individually to capture local delay variations. This local quality approach allows the system to guarantee maximum frequency operation (reliability) by accounting for worst-case scenarios in unique paths, while avoiding the bias of applying worst-case assumptions uniformly across the entire clock tree, thus improving overall measurement precision.
Data Source
AI summary
A set of respective first delay values for paths from a clock source to nodes of the integrated circuit is generated. Respective second delay values for the paths are generated from the clock source through the clock tree to the nodes. Each first delay value corresponds to one of the second delay values for one of the nodes, and each is greater than the corresponding second delay value. A set of common delay values is generated, with each common delay value being a delay for a shared portion of the paths from the clock source through the clock tree to two of the nodes. The determined clock skew is based on the first delay value for a first node, the second delay value for a second node, and the common delay value for the shared portion of the paths from the clock source to the first and second nodes.