Configurable Clock Skew Routing for IC Time Borrowing
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Solution Overview
Problem
Conventional time borrowing schemes in integrated circuits face limitations in achieving optimal performance due to limited clock network delays, complexity, and issues with race conditions and clock timing, particularly in accommodating the delays of slow logic paths without slowing down the entire circuit.
Innovation Solution
The implementation of an integrated circuit with multiple clock distribution networks and programmable routing and delay circuitry allows for intelligent placement of clock sources and adjustment of clock skews, enabling time borrowing by leveraging differences in clock delays across various networks to optimize circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional flip-flop-based sequential logic circuits are used with regular clock distribution, then ease of circuit design is improved, but circuit performance is limited due to the need to slow down clock frequency to accommodate the delay of the slowest combinational logic paths
Solution Approach 1:
The clock distribution network is segmented into multiple types (global, regional, peripheral) that cover different regions of the core logic with different delay characteristics. This segmentation allows different parts of the circuit to receive clock signals with appropriate delays, enabling time borrowing without requiring a uniform slow clock frequency across the entire circuit.
Solution Approach 2:
Different regions of the core logic receive clock signals with locally optimized delays. Logic circuits in overlapping regions can access multiple clock networks with different delay profiles, allowing each local region to operate with the clock timing best suited to its specific logic path requirements, thereby improving overall circuit performance while maintaining design regularity.
2Productivity
If conventional time borrowing schemes with limited clock network delays are used, then some performance improvement is achieved, but optimal performance cannot be obtained due to the limited number of delays available from the clock network
Solution Approach 1:
The system provides dynamically adjustable clock skew through programmable routing and delay circuitry. The amount of time borrowing and clock skew can be configured based on the specific timing requirements of different logic paths, allowing optimal performance adjustment rather than being constrained to fixed delay values. This dynamic configurability enables the clock distribution to adapt to various circuit performance requirements.
3Loss of time
If conventional time borrowing schemes are implemented, then time borrowing capability is provided, but the schemes are prone to problems associated with race conditions and clock timing issues
Solution Approach 1:
Programmable routing and delay circuitry serve as intermediaries between the clock source and the logic circuits. These intermediaries provide controlled and predictable delay adjustments, mediating the clock signal distribution to achieve time borrowing while maintaining reliable timing relationships. The programmable nature of these intermediaries allows precise control over clock skew, reducing the likelihood of race conditions and timing issues compared to conventional fixed delay schemes.
Data Source
AI summary
An integrated circuits with sequential logic circuitry is provided. The sequential logic circuitry may including latching circuits that receive clock signals from on-chip or off-chip clock sources. The clock signals may exhibit clock skew that is native to the integrated circuit. The natively existing clock skew can be leverage to perform time borrowing to help optimize circuit performance. The desired clock skew can be achieved by intelligent placement of the clock sources and deliberate routing of the clock signals from the clock sources to respective types of clock distribution networks on the integrated circuit.