Clock Skew Realignment Using Counter and Window Logic
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Solution Overview
Problem
Clock skew between multiple clock signals used in systems leads to undesirable increases in power and area when addressed using phase-locked loops (PLLs), necessitating an alternative method to maintain reliable phase relationships without additional PLLs.
Innovation Solution
A method involving a counter that generates a new second clock signal with a pulse aligned with the first clock signal, utilizing edge detect and window logic to realign clock signals without the need for a PLL, ensuring the desired phase relationship between plesiochronous or mesochronous signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase-locked loop (PLL) is used to regenerate clock signals to address clock skew, then the phase relationship between clock signals is maintained, but power consumption and area increase
Solution Approach 1:
The patent extracts only the essential function of PLL (phase alignment) and implements it using a counter and pulse generator that count cycles of the first clock signal and generate aligned pulses, eliminating the need for a full PLL circuit while maintaining phase synchronization
Solution Approach 2:
The patent creates a simplified copy of the PLL's phase alignment function using a counter that replicates the frequency division and phase synchronization capability without requiring the complex feedback loop and phase detector circuitry of a traditional PLL
2Reliability
If a phase-locked loop (PLL) is used to regenerate clock signals to address clock skew, then the phase relationship between clock signals is maintained, but area increases
Solution Approach 1:
The patent removes the unnecessary components of a full PLL (phase detector, voltage controlled oscillator, feedback loop) and retains only the essential cycle counting and pulse generation functionality, significantly reducing the circuit area while maintaining phase alignment
Solution Approach 2:
The patent replaces the expensive, complex PLL circuit with a simple counter and pulse generator that uses fewer logic elements and occupies less silicon area, achieving the same phase synchronization function with a more economical implementation
3Use of energy by stationary object
If clock signals are realigned using a counter and pulse generation method, then power consumption and area are reduced, but the complexity of detecting and measuring clock edges increases
Solution Approach 1:
The patent introduces an edge detect circuit as an intermediary component that simplifies the detection of clock signal transitions, providing clean digital signals to the counter and window logic without requiring complex detection circuitry in the main synchronization path
Data Source
AI summary
A system receives a first clock signal with a first frequency and a second clock signal having a second frequency lower than the first frequency. The system generates a new second clock signal aligned with the first clock signal based on a known phase/frequency relationship between the clock signals. A counter counts cycles of the first clock signal. The system generates a new second clock signal with an edge aligned with a first clock signal when the counter reaches a predetermined count value and the system resets the counter. A window opens that includes a time period when the edge of the first clock signal is expected. If an edge of the first clock signal is detected outside of the window, the counter is reset responsive to the detected edge.