Clock Skip Masking Across Multiple Domains to Minimize Voltage Noise
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Solution Overview
Problem
High-speed microprocessors face power consumption issues due to increased operating frequencies, leading to disparities between processor speed and memory access speed, necessitating methods to conserve power in multi-threaded processors while minimizing voltage noise.
Innovation Solution
Implementing a method that generates and adjusts skipped clock cycle signals across multiple domains of a microprocessor, using masked global clock signals to reduce effective operating frequency and manage voltage noise by prioritizing and spreading out changes to clock cycle skipping masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating frequency of the microprocessor is increased to improve processing speed, then the processing speed is improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic clock frequency adjustment by allowing different processor domains to operate at different clock frequencies. The clock control unit dynamically selects which clock cycles to gate based on current operational needs, enabling the system to adapt between high-speed operation and power-saving modes without fixed frequency constraints
Solution Approach 2:
The patent divides the processor into multiple domains (first domain and second domain) with independent clock control. Each domain can have its own clock gating pattern, allowing selective power management of different processor components based on their specific needs while maintaining overall system functionality
2Use of energy by moving object
If clock cycle skipping is implemented to reduce power consumption, then power consumption is reduced, but voltage noise increases
Solution Approach 1:
The patent applies different clock gating patterns to different domains based on their specific operational characteristics. The first domain and second domain can have different skip patterns, allowing the system to minimize voltage noise in critical areas while maintaining power savings in less sensitive areas
Solution Approach 2:
The clock control unit monitors the operational state and adjusts the clock gating pattern dynamically. When voltage noise becomes excessive, the system can modify which cycles are skipped or adjust the gating pattern to distribute noise more evenly across time
3Productivity
If multiple threads are executed concurrently to offset memory access downtime, then throughput is improved, but power consumption increases
Solution Approach 1:
The patent enables partial execution of thread instructions by allowing certain processor domains to remain active while others are clock-gated. This allows the system to maintain partial throughput capability while consuming less power, rather than fully activating all threads or completely shutting down
Data Source
AI summary
Implementations of the present disclosure involve an apparatus and/or method for providing one or more clock signals that include a skipped clock cycle to a portion of a computing system. The skipped cycle clock signals may be changed by the computing system during operation of the system by altering masks applied to a global clock signal. However, the flexibility to alter various skipped cycle clock signals may introduce noise or signal disruptions within the system. Thus, the present disclosure may also involve an apparatus and/or method for managing the altering of the clock cycle skipping masks to manage the voltage noise introduced into the system by the adjustment of the operating frequency of the portions of the system. In one embodiment, the method includes prioritizing or otherwise ordering the bits of the masks applied to the global clock signal to attempt to prevent similar bits from being altered simultaneously.