Clock Source Stability Optimization via Dual Reference Clocks
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Solution Overview
Problem
In high-real-time networks like headend stations, the short-term stability of clocks synchronized with reference clocks is compromised due to transmission delays and temperature changes, leading to inaccuracies and potential data packet loss.
Innovation Solution
A method that uses a free-running second reference clock to correct the clock source by controlling its frequency or phase, with the second reference clock serving as a corridor for the first reference clock's deviations, and employing phase-locked loops and averaging filters to minimize jitter and drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the clock source is synchronized with a long-term stable reference clock using NTP, then the long-term accuracy is improved, but the short-term stability deteriorates due to transmission delays and temperature changes
Solution Approach 1:
The patent divides the reference clock system into two independent parts: a long-term stable reference clock (e.g., GPS-disciplined oscillator) for accuracy and a short-term stable reference clock (e.g., temperature-compensated crystal oscillator) for stability. Each clock type compensates for the weaknesses of the other, resolving the contradiction between long-term accuracy and short-term stability.
Solution Approach 2:
The patent merges two previously separate clock sources into a unified clock system where the long-term stable reference clock and short-term stable reference clock work together. The phase-locked loop combines their outputs to produce a clock signal that exhibits both the long-term accuracy of the first clock and the short-term stability of the second clock.
2Measurement precision
If averaging and interpolation are used to synchronize the clock, then the long-term accuracy is improved, but the response time to temperature changes deteriorates due to processing delays
Solution Approach 1:
The patent introduces a short-term stable reference clock that proactively compensates for temperature-induced frequency changes before they significantly impact the clock output. This preliminary action occurs through the phase-locked loop continuously adjusting the clock frequency based on the stable reference, eliminating the need to wait for averaging to detect drift.
Solution Approach 2:
The phase-locked loop acts as an intermediary between the temperature-stable reference clock and the output clock signal. It rapidly processes frequency comparisons and applies corrections, providing a fast response mechanism that bypasses the slow averaging process while maintaining long-term synchronization accuracy.
3Device complexity
If a single reference clock is used for synchronization, then the system complexity is reduced, but the clock stability deteriorates due to cumulative time offsets
Solution Approach 1:
The patent segments the reference clock function into two specialized clocks: one optimized for long-term accuracy and another for short-term stability. This segmentation allows each clock to perform its specific function effectively, preventing the cumulative time offsets that occur when a single clock must compromise between conflicting requirements.
Solution Approach 2:
The patent creates a composite clock system by combining two different types of reference clocks with complementary characteristics. The long-term stable reference clock provides accuracy over extended periods, while the short-term stable reference clock maintains stability during rapid environmental changes, together forming a superior clock system.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the cumulative time offset and phase noise, enhancing the short-term stability of the clock source, thereby preventing data packet loss and ensuring reliable real-time operations.
Implementation Method 1
A further minimization of this statistical time delay is achieved by a phase-locked loop (PLL) integrated into the secondary server 3. In this PLL, the received times, which represent the clock cycles of the corresponding reference time source (and thus phases) counted in the NTP server from an initialization time until the respective transmission time, are compared with the clock cycles of the corresponding reference time source at the time the individual timestamp information is received in the secondary server 3 (which also represent phases). The phase-locked loop minimizes this phase jitter or phase noise by averaging over several phase differences in an averaging filter.
Data Source
AI summary
A system for optimizing short-term stability of a clock from a clock source synchronized with a first reference clock source with long-term stability transmits numbers of clocks of a first reference clock from the first reference clock source (21, 22, 23, 24) to the clock source (8) between an initialization time and a plurality of times in each case in a data-packet-oriented network (9). The clock from the clock source (8) is adjusted by correcting a difference between numbers of clocks of the first reference clock which are received in the clock source (8) and numbers of clocks of the first reference clock between the initialization time and the respective times at which the numbers of clocks of the first reference clock are received. In addition, numbers of clocks of a second reference clock for the data packet are transmitted to the clock source (8) at individual times with the number of clocks from at least one second freewheeling reference clock source (111, 112). The maximum difference between the first reference clock and the second reference clock from the clock source (8) is known. The difference between the clock from the clock source (8) and each second reference clock is limited to a first adjustable threshold value.