Clock Source Switching Circuit Without Glitches or Truncated Pulses
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Solution Overview
Problem
Existing clock multiplexer systems generate glitches when switching between clock sources, disrupting phase alignment and pulse ratio in serializer-deserializer systems, especially when one clock source is stopped during selection.
Innovation Solution
A clock-switching circuit with two switches, one for lower frequency and one for higher frequency clock sources, using delay flip-flops and logic gates to generate control signals that prevent glitches by ensuring continuous output and maintaining phase alignment and pulse ratio through synchronized enable and disable signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple clock multiplexer is used to switch between clock sources, then the device complexity is reduced, but glitches are generated on the output line when the select line is toggled
Solution Approach 1:
The patent applies preliminary action by stopping clock two before clock one is enabled during the switching transition. The select signal is synchronized to clock one's rising edge, and clock two is stopped one cycle before the transition occurs. This preliminary stopping prevents the glitch that would otherwise occur when both clocks are active simultaneously during switching.
2Reliability
If clock two is stopped when the select signal is toggled to achieve glitch-free output, then output signal quality is improved, but the output clock signal may be lost if clock one is also stopped
Solution Approach 1:
The patent ensures continuous output availability by stopping clock two preliminarily (one cycle before switching) rather than simultaneously with the select signal toggle. This timing arrangement guarantees that clock one is already running and ready to provide output before clock two is completely stopped, preventing any output gap while still achieving glitch-free transition.
3Productivity
If multiple synchronous clocks are multiplexed with phase alignment requirements, then the system performance is improved, but the device complexity increases
Solution Approach 1:
The patent merges the phase alignment function into the existing clock multiplexer structure by using the same select signal synchronization mechanism. Instead of adding separate phase alignment circuits, the invention combines multiple functions (clock selection, glitch prevention, and phase alignment) into a unified switching mechanism that operates on the rising edge of the selected clock.
Data Source
AI summary
A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.