Two-phase clock-stalling for timing error detection in IC blocks
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Solution Overview
Problem
Existing circuit designs face challenges in detecting and correcting timing errors due to the performance and layout overhead associated with error detection and correction circuits, particularly in integrated circuits (ICs), where timing delay errors can lead to reduced performance and overdesign, and existing solutions like double data sampling registers (DDSRs) impose significant physical and performance losses.
Innovation Solution
The system partitions the circuit into independently clocked blocks, integrates error signal propagation circuits, and implements a two-phase error correction mechanism using double data sampling registers (DDSRs) to detect and correct timing errors with minimal impact on circuit behavior, allowing for error recovery and resynchronization across blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If double data sampling registers (DDSRs) are used for error detection and correction, then timing errors can be detected and corrected, but the circuit overhead and performance loss increase significantly
Solution Approach 1:
The circuit is divided into independently clocked blocks, each with its own clock signal that can be stalled independently. This segmentation allows error correction to be performed locally without affecting the entire circuit, reducing the overall circuit overhead while maintaining error detection and correction capabilities.
Solution Approach 2:
The patent implements dynamic clock stalling where the clock signal can be paused temporarily during error correction operations. This dynamic adjustment allows the circuit to adapt its timing behavior based on whether errors are present, enabling error correction without permanently increasing circuit complexity or affecting normal performance.
2Reliability
If the clock frequency is lowered to accommodate timing delay errors, then timing errors can be prevented, but the performance level of the IC is sacrificed
Solution Approach 1:
The patent uses dynamic clock stalling that temporarily pauses the clock signal only when and where errors occur, rather than permanently lowering the clock frequency for the entire circuit. This allows the circuit to maintain high performance during normal operation while preventing timing errors during error conditions through localized, temporary clock pauses.
3Reliability
If existing DDSR solutions are implemented, then error detection and correction can be performed, but significant performance loss occurs when flushing the pipeline
Solution Approach 1:
By segmenting the circuit into independently clocked blocks, the patent enables error correction to be performed locally within each block without requiring a full pipeline flush. This localized approach allows other parts of the circuit to continue operating normally, significantly reducing the time loss associated with error correction compared to traditional pipeline flushing methods.
Data Source
AI summary
One embodiment of the present invention provides a system that augments a circuit design with a mechanism for detecting and correcting timing errors. This system first partitions the circuit into a set of blocks that are clocked by an independent clock source, and integrates an error signal propagation circuit between the set of blocks. For a respective block, the system determines a set of internal registers that are to be implemented as double data sampling registers, and replaces the determined set of internal registers with double data sampling registers, wherein a given double data sampling register is configured to generate an error signal when it detects a timing error. Then, the system integrates a two-phase error correction circuit into the respective block, wherein when notified of a timing error by a double data sampling register, the two-phase error correction circuit is configured to stall registers in the respective block.