Clock Generation Circuit Standby Bias for Fast Startup
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Solution Overview
Problem
Current clock generation circuits face challenges in achieving a high frequency clock generation with low power consumption and fast start-up times, as existing approaches fail to reduce power consumption by 90% while maintaining a start-up time of approximately 1.5 microseconds to return to full operating mode.
Innovation Solution
A clock generation circuit operates in three modes: ON, OFF, and STANDBY, where in STANDBY mode, a small bias current is applied to internal nodes to reduce transient perturbations, allowing for very fast startup times from STANDBY to ON, enabling the circuit to be placed in STANDBY mode more frequently and reducing overall power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the clock generation circuit is completely shut down to save power, then power consumption is reduced, but start-up time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-charging internal nodes to their operating voltages during standby mode using bias circuits. This prepares the circuit in advance so that when transitioning to ON mode, only minimal additional charging is needed, achieving fast start-up (1.5 microseconds) while maintaining power savings (90% reduction) during standby.
2Use of energy by moving object
If clock frequency is reduced to lower power consumption, then power savings are achieved, but performance degradation occurs
Solution Approach 1:
The patent implements dynamics by enabling the clock generation circuit to dynamically transition between three modes (ON, STANDBY, OFF) based on real-time performance requirements. The circuit can quickly switch between full performance mode and power-saving modes, allowing performance to be maintained when needed while achieving power savings during low-activity periods.
3Productivity
If the clock generation circuit operates in full power mode, then performance is maximized, but power consumption increases
Solution Approach 1:
The patent applies parameter changes by modifying the bias current parameters applied to internal nodes based on the operational mode. During standby mode, reduced bias current parameters are applied to minimize power consumption while maintaining the ability to quickly transition to full power mode when performance is required, achieving a 90% power reduction during standby.
Data Source
AI summary
A clock generation circuit operates in a STANDBY mode as well as conventional OFF and ON modes. In STANDBY mode, a small pre-bias current is applied to amplifiers in the clock generation circuit, which bias voltages on internal nodes to very near their operating voltage values. This reduces transient perturbations on signals as the clock generation circuit is returned to ON mode. The smaller transients settle faster, and allow the clock generation circuit to achieve very fast startup times from STANDBY to ON. The very fast startup times allow the clock generation circuit to be placed in STANDBY mode more often, such as when a system must monitor and rapidly respond to activity on an external bus or interface (such as an RF modem).