Clock Stoppage in Multi-Domain Integrated Circuits
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Solution Overview
Problem
In silicon debug processes, particularly in integrated circuits with multiple asynchronous clock domains, stopping one clock domain deterministically may not guarantee enough debug information, and stopping a single large clock domain can cause voltage transients, leading to loss of debug information in state elements.
Innovation Solution
The implementation of a circuit and method that allows for the synchronized stopping of multiple internal clocks with different levels of determinism, using clock groups and multiplexers to control the clock stop process, ensuring that clocks are stopped in a user-defined order to prevent data loss and ensure connectivity for scan-based shifting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single large clock domain is stopped at its root, then clock stoppage is achieved, but voltage transients occur causing loss of debug information
Solution Approach 1:
The patent divides the clock system into multiple independent clock domains, each with its own stop control. Instead of stopping one large clock domain that causes voltage transients, the system stops multiple smaller clock domains separately. This segmentation allows debug information to be captured from each domain independently without the harmful voltage effects of stopping a single large domain.
2Reliability
If one clock domain is stopped deterministically, then clock control is achieved, but not enough debug information is obtained from other domains
Solution Approach 1:
The patent creates a universal clock stop control mechanism that can stop multiple clock domains through a coordinated sequence. The controller manages multiple clock domains universally, stopping them in a determined sequence while maintaining the ability to capture debug information from all domains. This multi-functional approach ensures both deterministic control and complete debug information collection.
Solution Approach 2:
The patent uses preliminary action by capturing debug information from each clock domain before stopping it. The controller sequences the operation to first capture data from a domain, then stop that domain's clock. This preliminary capture ensures debug information is preserved before the clock stoppage occurs, addressing the completeness issue while maintaining deterministic control.
3Loss of information
If multiple asynchronous clock domains are stopped simultaneously, then debug information from all domains is captured, but lack of synchronization causes data loss
Solution Approach 1:
The patent applies preliminary action by capturing debug information from each clock domain before stopping its clock. The controller sequences operations to first capture data, then stop the clock for that domain. This ensures data is preserved before clock stoppage, preventing data loss while maintaining data integrity through proper sequencing.
Solution Approach 2:
The patent introduces a controller as an intermediary that manages the stopping sequence of multiple asynchronous clock domains. This intermediary coordinates the capture and stop operations, ensuring that each domain's data is captured before its clock is stopped. The controller mediates between the need for complete data capture and the need to maintain data integrity across asynchronous domains.
Data Source
AI summary
Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain. The select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative clock input of the first clock multiplexer for an alternative clock signal from the controller.