Programmable Clock Stretching for At-Speed IC Debugging
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Solution Overview
Problem
Conventional speed-path debugging techniques for integrated circuits (ICs) are time-intensive and resource-heavy, often requiring extensive iterations of scan dumps and laser probing, which can be destructive and inefficient, especially when detecting setup timing issues that arise between pre-silicon and post-silicon results.
Innovation Solution
The integration of clock stretching circuitry within ICs, featuring programmable clock controllers and a trigger circuit that can dynamically implement a clock stretch mode, reducing the frequency of clock signals to facilitate faster debugging without rebooting or reinitializing the IC, thereby reducing test and debug time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional speed-path debugging techniques (scan dumps and laser probing) are used, then setup timing issues can be detected, but the process is time-intensive and requires extensive iterations
Solution Approach 1:
The patent implements dynamic clock stretching where the clock frequency is programmably reduced during specific cycles to slow down timing-critical paths. This allows observers to capture setup timing issues that occur at normal operating speed by stretching those specific clock cycles, converting a static debugging approach into a dynamic one that adapts timing to diagnostic needs.
Solution Approach 2:
The invention changes the clock frequency parameter dynamically during operation. By programmably reducing the clock frequency for selected cycles without stopping the IC, the system modifies the timing parameters of the circuit under test, allowing observation of setup violations that would be too fast to capture at full operating speed.
2Measurement precision
If conventional debugging techniques are used, then faults can be identified, but extensive iterations of scan dumps and laser probing are required
Solution Approach 1:
The system performs preliminary action by programmably reducing clock frequency in advance of the actual fault detection moment. The clock stretch mode is enabled before the problematic cycle occurs, allowing the timing issues to be captured during normal operation without requiring iterative scan dumps or destructive laser probing.
Solution Approach 2:
The debugging system serves itself by using the IC's own clock control infrastructure to facilitate debugging. The programmable clock controllers and trigger circuits within the IC enable self-diagnosis of timing issues without requiring external debugging equipment or destructive testing methods.
3Measurement precision
If clock frequency is reduced to slow down timing-critical paths, then setup timing issues become observable, but the IC operation is slowed down
Solution Approach 1:
The system applies periodic action by stretching only specific clock cycles that are suspected of containing timing issues, rather than continuously slowing the clock. The trigger circuit detects specific conditions and enables clock stretch mode only for those particular cycles, maintaining normal operating speed for all other cycles.
Solution Approach 2:
The clock frequency is made dynamic rather than static. The system switches between normal frequency and stretched frequency based on real-time conditions detected by the trigger circuit. This allows the IC to operate at full speed most of the time while temporarily slowing down only when diagnostic information is needed.
4Adaptability or versatility
If programmable clock controllers and trigger circuits are added to enable dynamic clock stretching, then debugging capability is improved, but device complexity increases
Solution Approach 1:
The clock controllers serve multiple functions: they generate normal operating clocks and also implement clock stretching for debugging. The trigger circuits serve dual purposes by both detecting timing conditions and controlling the clock stretch mode. This multi-functionality reduces the need for separate dedicated debugging hardware.
Solution Approach 2:
The IC uses its own existing clock control infrastructure to provide debugging capabilities. Rather than adding completely separate debugging hardware, the system repurposes the programmable clock controllers and trigger circuits already present in modern ICs, allowing them to serve both operational and diagnostic functions.
Data Source
AI summary
An integrated circuit can include one or more clock controllers. Each clock controller corresponds to a different clock signal of a set of one or more clock signals of the integrated circuit. Each clock controller is configured to implement a clock stretch mode that generates a modified clock signal having a frequency that is less than the clock signal. The integrated circuit can include a trigger circuit configured to enable selected ones of the one or more clock controllers to implement the clock stretch mode. The trigger circuit and the one or more clock controllers are hardwired and are programmable using control infrastructure circuitry of the integrated circuit.