Clock Stretching for Timing Violation Prevention in Latch Circuits
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Solution Overview
Problem
Digital logic systems face timing violations due to voltage drops, temperature variations, and manufacturing process corners, leading to errors and reduced operation frequency, with existing solutions either slowing down the system or requiring additional logic for correction.
Innovation Solution
The apparatus and method involve a clock signal with alternating levels, a detecting means to identify timing violations, and a time stretching mechanism to delay the clock, ensuring latches are closed at the appropriate level, thereby preventing false timing violations and mitigating timing errors without reducing overall system frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing margins are applied to avoid timing violations, then reliability is improved, but productivity deteriorates due to reduced operation frequency
Solution Approach 1:
The patent applies preliminary action by detecting potential timing violations before they cause errors and proactively stretching the clock cycle to prevent them. The detection mechanism identifies at-risk timing scenarios in advance, and the clock stretching is applied preemptively to ensure correct operation before the violation occurs.
Solution Approach 2:
The patent implements dynamics by making the clock cycle duration variable rather than fixed. The clock stretching mechanism dynamically extends the clock cycle only when timing violations are detected, allowing the system to adapt its timing characteristics in real-time based on actual operating conditions, thus maintaining high frequency when possible while ensuring reliability when needed.
2Reliability
If buffers are added to prevent false timing violations, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses the clock signal itself as an intermediary to resolve timing issues. Instead of adding buffers between logic stages, the invention mediates the timing relationship by stretching the clock cycle, which indirectly adjusts the timing of all clocked elements without requiring additional buffering components.
Solution Approach 2:
The patent applies parameter changes by modifying the clock cycle duration parameter dynamically. Rather than changing the physical structure or adding components like buffers, the invention changes the temporal parameter of the clock signal to prevent false timing violations, thereby maintaining simplicity while improving reliability.
3Reliability
If system frequency is reduced to accommodate slow combinational logic, then timing violations are avoided, but productivity deteriorates
Solution Approach 1:
The patent implements dynamics by making the clock cycle duration variable rather than fixed. The clock stretching mechanism dynamically extends the clock cycle only when timing violations are detected, allowing the system to adapt its timing characteristics in real-time based on actual operating conditions, thus maintaining high frequency when possible while ensuring reliability when needed.
Solution Approach 2:
The patent applies preliminary action by detecting potential timing violations before they cause errors and proactively stretching the clock cycle to prevent them. The detection mechanism identifies at-risk timing scenarios in advance, and the clock stretching is applied preemptively to ensure correct operation before the violation occurs.
Data Source
Figure 1~7b
Figure 2
Figure 3
AI summary
An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.