Clock Stretching With Latch-Based Timing Violation Prevention
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Solution Overview
Problem
Digital logic systems face timing violations due to voltage drops, temperature variations, and manufacturing process corners, leading to errors and reduced operation frequency, with existing methods either slowing down the system or requiring additional logic and power consumption.
Innovation Solution
The solution involves an apparatus and method that uses a clock signal with alternating levels and latches clocked at inverse times to detect and mitigate timing violations by stretching the clock cycle, preventing false timing violations and reducing the need for buffers and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If timing margins are applied to avoid timing violations, then reliability is improved, but productivity deteriorates due to reduced operation frequency
Solution Approach 1:
The patent applies preliminary action by detecting potential timing violations before they cause errors through proactive monitoring mechanisms. The system continuously checks for timing margin violations and preemptively corrects them by adjusting clock signals, preventing the need for conservative timing margins that would reduce operation frequency.
Solution Approach 2:
The patent implements feedback mechanisms that monitor actual timing performance and use this information to dynamically adjust clock signals. By feeding back timing violation detection results to the clock stretching mechanism, the system can maintain high operation frequency while ensuring reliability through real-time corrections rather than static timing margins.
2Reliability
If conventional timing error detection methods are used, then reliability is improved, but device complexity increases due to additional logic circuits
Solution Approach 1:
The patent applies universality by designing the clock stretching mechanism to serve multiple functions: it acts as both a timing violation detector and a corrective action generator. The same clock control logic that manages normal operation also detects and corrects timing violations, eliminating the need for separate detection circuits and reducing overall device complexity.
Solution Approach 2:
The system applies self-service by enabling the clock control mechanism to automatically detect and correct its own timing issues without external intervention or additional monitoring circuits. The clock stretching logic monitors its own output and self-corrects timing violations, reducing the need for separate detection and correction hardware.
3Reliability
If buffers are added to prevent false timing violations, then reliability is improved, but use of energy increases due to additional power consumption
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting clock signal parameters (timing and stretching) rather than adding static buffering hardware. By changing the temporal parameters of the clock signal based on detected timing violations, the system prevents false timing violations without the continuous power consumption associated with buffer circuits.
4Reliability
If clock stretching is applied to mitigate timing violations, then reliability is improved, but productivity deteriorates due to clock cycle delay
Solution Approach 1:
The patent applies dynamics by making the clock stretching amount variable rather than fixed. The system dynamically adjusts the degree of clock stretching based on the severity and type of timing violation detected, applying minimal necessary correction to maintain reliability while preserving maximum operation frequency. This dynamic adjustment prevents excessive slowing of the clock cycle.
Data Source
AI summary
An apparatus, comprising a clock adapted to provide a clock signal alternating with a cycle between a first level and a second level if a timing violation is not detected; a first latch adapted to be clocked such that it passes a first signal when the clock signal is at the first level; a second combinational logic adapted to output a second signal based on the first signal passed through the first latch; a second latch adapted to be clocked such that it passes the second signal when the clock signal is at the second level; a detecting means adapted to detect the timing violation of at least one of the first signal and of the second signal; a time stretching means adapted to stretch, if the timing violation is detected, the clock such that the clock alternates between the first level and the second level with a delay.