Clock Supply Circuit Reducing Oscillation Stabilization Time
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock supply circuits require a lengthy oscillation stabilization waiting time, which delays the startup and initialization of LSIs, as they rely on quartz oscillators that take several milliseconds to tens of milliseconds to stabilize, affecting the operational readiness of microcontrollers and other integrated circuits.
Innovation Solution
A clock supply circuit incorporating an analog filter to remove pulses with shorter pulse widths and a divider to output a stable clock signal, allowing the system to initiate operations earlier by ensuring the oscillation stabilization waiting counter and subsequent circuits can operate accurately with a divided clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a quartz oscillator is used to supply clock signals, then the LSI can operate with a stable clock signal, but the oscillation stabilization waiting time becomes lengthy (several milliseconds to tens of milliseconds)
Solution Approach 1:
The patent applies preliminary action by performing oscillation stabilization counting during the startup phase before the LSI begins normal operation. The counter 306 counts clock pulses from the beginning, and the system determines when oscillation has stabilized without requiring a separate waiting period, thus eliminating the time loss while ensuring reliability
Solution Approach 2:
The system uses its own internal counter 306 and clock signal to monitor and determine oscillation stabilization status autonomously. The LSI self-detects when the quartz oscillator has stabilized by counting clock pulses and comparing against a predetermined threshold, eliminating the need for external reset signals or additional stabilization waiting time
2Reliability
If the oscillation stabilization waiting time is extended to ensure stable clock signal, then the clock signal becomes reliable, but the LSI startup time and operational readiness are delayed
Solution Approach 1:
The patent implements feedback by continuously monitoring the clock signal characteristics through counter 306 during startup. The system counts clock pulses and uses this feedback information to determine when oscillation has stabilized, allowing the LSI to begin operation at the optimal moment without unnecessary delays, thus improving productivity while maintaining reliability
Solution Approach 2:
The system dynamically adjusts the startup timing based on actual oscillation stabilization status. Rather than using a fixed waiting period, the counter 306 continuously monitors clock pulses and enables LSI operation as soon as the predetermined count is reached, allowing the system to adapt to varying oscillation characteristics and minimize startup time while ensuring stability
Data Source
AI summary
An object is to provide a clock supply circuit capable of supplying a clock signal with a short oscillation stabilization waiting time. There is provided a clock supply circuit having a filter removing from a first clock signal pulses having a shorter pulse width than a threshold value and passing pulses having a longer pulse width than the threshold value to thereby output a second clock signal; and a divider dividing the second clock signal to thereby output a third clock signal.