Clock Supply Switching for Over-Voltage Input Switches
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Solution Overview
Problem
Integrated circuits face challenges in handling input signal voltages that exceed the IC supply voltage range, particularly when these voltages vary significantly, as existing switched-capacitor circuits struggle to maintain accurate analog measurements and prevent device overstressing due to limitations in clock voltage levels and switch conduction efficiency.
Innovation Solution
The implementation of a clock selector and level shifter system that dynamically switches between IC supply voltage and input signal voltage as the alternative supply, ensuring low-impedance conduction and preventing switch anomalies, by using an over-voltage detector to control the selection of clock signals for input switches, thereby maintaining efficient operation across a wide voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If switched-capacitor circuits are used for analog signal processing with input voltages exceeding IC supply voltage, then the circuit can handle over-voltage conditions, but clock voltage level limitations cause switch conduction efficiency to degrade and measurement precision to worsen
Solution Approach 1:
The patent implements dynamic clock signal selection where the clock voltage level is adjusted based on the input signal voltage level. When input voltage exceeds the IC supply voltage, a level-shifted clock signal is used; when input voltage is within the IC supply range, the standard clock signal is used. This dynamic adaptation resolves the contradiction by ensuring optimal switch conduction efficiency across the full voltage range, maintaining measurement precision while extending voltage handling capability.
Solution Approach 2:
The patent changes the clock voltage parameter dynamically based on operating conditions. A level shifter circuit generates a clock signal with voltage level shifted to match the input signal voltage when over-voltage conditions occur. This parameter change ensures that the clock signal maintains appropriate voltage levels for reliable switch conduction, preventing degradation in measurement precision while enabling extended voltage range operation.
2Adaptability or versatility
If dynamic voltage handling is implemented to cover wide voltage ranges, then adaptability improves, but device complexity increases due to additional clock selection and level shifting circuitry
Solution Approach 1:
The patent implements a universal clocking system that can operate in multiple voltage domains. The clock selector circuit chooses between the standard IC clock signal and the level-shifted clock signal based on voltage conditions, making the system multi-functional. This universal approach allows the same circuit architecture to handle both normal and over-voltage conditions without requiring separate dedicated circuits, thereby limiting the increase in device complexity while maintaining wide voltage range adaptability.
Solution Approach 2:
The patent introduces a level shifter circuit as an intermediary component that adapts the clock signal voltage level to match the input signal voltage. This intermediary element enables smooth transition between different voltage domains without requiring complex reconfiguration of the entire circuit. The level shifter acts as a buffer that simplifies the overall system architecture while enabling extended voltage range operation.
3Reliability
If standard IC supply voltage is used for clocking, then device operation is simple and reliable, but input signal voltages exceeding supply voltage cause switch anomalies and conduction failures
Solution Approach 1:
The patent implements dynamic clock voltage adjustment where the system automatically adapts the clock signal voltage level based on the input signal voltage. When the input voltage exceeds the IC supply voltage, the system switches to a level-shifted clock signal with higher voltage level. This dynamic response maintains reliable switch conduction across the full input voltage range, resolving the contradiction between conduction reliability and voltage range adaptability.
Solution Approach 2:
The patent employs voltage detection and feedback mechanisms that monitor the input signal voltage level and control the selection between standard and level-shifted clock signals. This feedback system ensures that the appropriate clock voltage level is applied based on real-time voltage conditions, maintaining reliable switch conduction while enabling extended input voltage range operation.
Data Source
AI summary
In an integrated circuit having input circuitry whose positive and/or negative input signals are gated by one or more clocked input switches, the switch clock signal CLK_SW used to clock the input switch(es) is automatically generated based on the higher of the IC's power supply voltage VDD and the positive input signal voltage Vplus. In one embodiment, a clock level shifter shifts an input clock signal CLK_VDD from the VDD voltage domain to generate a level-shifted clock signal CLK_VPLUS in the Vplus voltage domain. Based on a control signal VSEL, a clock selector selects either the input clock signal or the level-shifted clock signal to be the switch clock signal. An over-voltage detector generates both the logic state and the voltage domain of the control signal based on the higher of VDD and Vplus, such that the input switches are appropriately clocked even during over-voltage conditions in which Vplus>VDD.