Multi-Output Clock Supply Capacitance for Phase Shift Reduction
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Solution Overview
Problem
The existing clock generation circuitry in wireless devices experiences phase shifts due to varying undershoot in supply voltage when multiple RF clock buffers are active, leading to performance degradation in RF chips.
Innovation Solution
A capacitor array is used to selectively couple capacitive elements to the supply node based on the quantity of active clock buffers, reducing the variation in undershoot and phase shift of clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock buffers are used to generate multiple RF clock signals, then the functionality and performance of RF chips are improved, but phase shift occurs due to varying undershoot in supply voltage
Solution Approach 1:
The patent implements a dynamic capacitor array that can be selectively activated based on the number of active clock buffers. When more clock buffers are active, additional capacitors are coupled to the supply node to compensate for increased undershoot, thereby dynamically adjusting the supply voltage stability to maintain consistent clock signal phases across different operating conditions
Solution Approach 2:
The patent changes the capacitive loading parameter at the supply node by selectively coupling different numbers of capacitive elements based on the activity level of clock buffers. This parameter adjustment compensates for variations in undershoot, ensuring stable supply voltage and consistent clock signal phases regardless of how many clock buffers are active
2Reliability
If large on-chip capacitive elements are used to reduce phase shift, then clock signal stability is improved, but area consumption and cost increase
Solution Approach 1:
The patent divides a large capacitive requirement into multiple smaller capacitive elements arranged in an array. Instead of implementing one large capacitor that would consume significant chip area, the solution uses multiple smaller capacitors that can be selectively activated, achieving the same effective capacitance with reduced total area and lower cost
Solution Approach 2:
The patent makes the capacitive array dynamic by selectively coupling capacitive elements based on the number of active clock buffers. This dynamic configuration allows the system to use only the necessary capacitance for each operating condition, avoiding the area overhead of permanently implementing maximum capacitance and enabling area-efficient phase shift reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces the phase shift associated with clock signals, improving the operation of RF chips while minimizing cost and area consumption by eliminating the need for large on-chip capacitive elements.
Implementation Method 1
A capacitor array may be used to reduce a phase shift associated with clock signals generated by the clock buffers
Data Source
AI summary
Certain aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to power supply inputs of the plurality of clock generation circuits. The circuit may also include a capacitor array coupled to the output of the power supply circuit and include a plurality of capacitive elements, the capacitor array being configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.