Clock Suppression Circuitry for At-Speed Scan Testing
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Solution Overview
Problem
Scan testing of integrated circuits faces challenges due to multi-cycle propagation and false paths, which can result in indeterminate results during at-speed testing, as existing technologies fail to guarantee accurate latching of scan results.
Innovation Solution
The integration of clock suppression circuitry that selectively suppresses either the launch or capture pulses in scan latches associated with multi-cycle or false propagation paths, ensuring determinant scan results by controlling the clock signals during the testing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If at-speed scan testing is performed without clock suppression, then testing speed is improved, but indeterminate results occur due to multi-cycle propagation and false paths
Solution Approach 1:
The patent applies preliminary action by suppressing the launch pulse before it reaches scan latches associated with multi-cycle or false propagation paths. This preventive measure ensures that indeterminate results are avoided before they can occur, allowing at-speed testing to proceed without compromising result determinacy. The clock suppression circuitry is configured to selectively block launch pulses to specific scan latches based on their association with multi-cycle or false paths.
2Reliability
If clock suppression circuitry is added to suppress launch pulses, then result determinacy is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by implementing clock suppression selectively only at scan latches associated with multi-cycle or false propagation paths, rather than uniformly across all scan latches. The clock suppression circuitry is configured to identify and suppress launch pulses only where needed, maintaining result determinacy while minimizing the addition of circuit complexity. This localized approach ensures that the suppression functionality is added only where it is necessary to prevent indeterminate results.
Data Source
AI summary
An integrated circuit includes clock suppression circuitry that can suppress the launch pulse of an at-speed test to prevent scan test data from propagating from an output of a scan latch through a multi-clock cycle combinational logic path to a downstream scan latch during the at-speed test. The integrated circuit can also suppress the capture pulse of an at-speed test to prevents scan test data that is propagated from an upstream scan latch through a multi-cycle combinational logic path from being latched at the downstream latch during the at-speed test.