Clock Swallowing Pattern Control for Fast Frequency Transitions

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Solution Overview

Problem

Existing methods for adjusting clock signal frequencies, such as phase locked loops and fractional clock dividers, are inadequate for applications requiring fast transitions due to long relock times and high jitter, which can cause data sampling errors and timing issues in high-speed circuits.

Innovation Solution

The implementation of a clock swallowing device that selectively swallows pulses in a clock signal based on a repeating pattern defined by a sequence of numbers, allowing for rapid frequency adjustments with minimal jitter, using a counter, comparison circuit, and clock swallower to achieve desired clock frequencies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If phase locked loops or fractional clock dividers are used for frequency adjustment, then frequency control capability is provided, but transition time increases and jitter increases

Engineering Contradiction:
Improvefrequency transition speedVSAvoidsignal quality (jitter)
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The frequency adjustment process is segmented into discrete pulse swallowing events rather than continuous adjustment. The clock signal is divided into individual pulses, and specific pulses are selectively swallowed (removed) to achieve frequency reduction. This segmentation enables rapid transitions without the relock time issues of phase locked loops.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The clock swallowing operation operates periodically by counting clock pulses and swallowing pulses at predetermined intervals defined by a swallow ratio. This periodic action maintains regular timing patterns and minimizes jitter while enabling fast frequency transitions through simple counter-based control.

Inventive Principle:
Principle #19Periodic action

2Temperature

If clock frequency is reduced to control temperature, then temperature control capability is provided, but dynamic power consumption reduction causes voltage noise

Engineering Contradiction:
Improvechip temperatureVSAvoidvoltage noise
Core Design Contradiction:
TemperatureVSObject-generated harmful factors

Solution Approach 1:

Instead of uniformly reducing clock frequency across the entire system, the invention applies selective pulse swallowing to specific clock cycles. This local quality approach allows precise control of power consumption reduction, enabling temperature management while minimizing abrupt changes that cause voltage noise. The swallow ratio can be dynamically adjusted to match thermal requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The clock swallowing device dynamically adjusts the swallow ratio based on temperature feedback. When temperature increases, the swallow ratio increases to reduce power consumption; when temperature decreases, the swallow ratio decreases to maintain performance. This dynamic adaptation smooths power transitions and reduces voltage noise while maintaining effective temperature control.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9582027B2Clock swallowing device for reducing voltage noise
Publication Date: 2017.02.28 QUALCOMM INC
  • US9582027B2 patent drawing
  • US9582027B2 patent drawing
  • US9582027B2 patent drawing

AI summary

Systems and methods for controlling a frequency of a clock signal by selectively swallowing pulses in the clock signal are described herein. In one embodiment, a method for adjusting a frequency of a clock signal comprises receiving the clock signal, and swallowing pulses in the clock signal according to a repeating clock-swallowing pattern, wherein the pattern is defined by a sequence of numbers.