Low-Swing Clock Sequential Circuits With Full-Range Data Output
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Solution Overview
Problem
High power consumption in digital integrated circuits due to large and complex clock propagation networks, where clock signals toggle every clock cycle, often accounting for 50% or more of the overall power consumption, is a challenge that existing technologies have not adequately addressed.
Innovation Solution
Implementing low voltage clock swing sequential circuits by coupling input signals to transistors in a specific configuration, allowing the clock signal to have a reduced voltage swing, which reduces power consumption by enabling transistors to swing to the full voltage range even when the clock logic high level is below the supply voltage, thereby minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal swings to the full voltage range, then the sequential circuit can reliably capture and launch data, but the power consumption increases significantly
Solution Approach 1:
The patent changes the voltage parameter of the clock signal from full supply voltage swing to a reduced voltage swing (e.g., from 0 to VDD to 0 to VDD/2). This parameter change reduces the power consumption of the clock tree while maintaining reliable operation of sequential elements through the use of enabling transistors that ensure proper data capture and launch even with the reduced clock swing.
2Area of stationary object
If the clock tree is made large and complex to distribute clocks over the semiconductor area, then all sequential elements can be controlled, but the power consumption and device complexity increase
Solution Approach 1:
The patent reduces the voltage swing parameter of the clock signal throughout the clock tree, which directly reduces the power consumption of the clock distribution network. The reduced voltage swing is propagated through the clock tree, allowing extensive clock distribution coverage while minimizing the power consumed by the clock tree itself.
Solution Approach 2:
The patent segments the clock distribution into a clock tree network that carries the reduced voltage swing clock signal to multiple sequential elements. Each sequential element is equipped with enabling transistors that segment the data path control, allowing the clock to effectively control transitions despite the reduced voltage swing.
3Use of energy by moving object
If the clock logic high level is reduced below the supply voltage level, then power consumption decreases, but the output data signal may not swing to the full voltage range
Solution Approach 1:
The patent introduces enabling transistors (e.g., PMOS transistors controlled by the clock signal) as intermediary elements between the clock signal and the data paths. These enabling transistors act as mediators that use the reduced voltage swing clock signal to control the switching of data, ensuring that the output data signal can still swing to the full voltage range even though the clock itself has a reduced voltage swing.
Solution Approach 2:
The patent creates an asymmetric relationship between the clock signal voltage swing and the data signal voltage swing. The clock signal operates at a reduced voltage level (asymmetric from the full supply voltage), while the data signals maintain the full voltage range through the action of enabling transistors that are controlled by the asymmetric clock signal.
Data Source
AI summary
Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.