Clock Switch Gate Biasing for Low-Leakage Resonant Clocking
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Solution Overview
Problem
Existing clocking systems face inefficiencies due to high power consumption, particularly in battery-operated devices and server farms, caused by leakage current and resistive or capacitive loading, which is exacerbated by the tradeoff between resonant and conventional modes of operation.
Innovation Solution
The use of high impedance voltage sources to drive the gate terminals of a switch in a clocking system, reducing on-resistance and leakage by maintaining a near-constant gate overdrive voltage, and relocating the mode switch to optimize gate overdrive and reduce conducting resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional clocking systems are used, then clocking function is provided, but power consumption is high due to leakage current and resistive loading
Solution Approach 1:
The patent changes the impedance parameter of the voltage sources driving the transistor gates from low to high impedance. This parameter change reduces the capacitive loading on the clock node, thereby reducing power consumption while maintaining reliable clocking operation through the resonant LC circuit
Solution Approach 2:
The patent employs resonant oscillation at a specific frequency, utilizing periodic action of the LC circuit to generate clock signals. This resonant periodic action enables efficient energy transfer and reduces power consumption compared to conventional non-resonant clocking methods
2Loss of energy
If resonant mode is used to reduce power consumption, then efficiency improves, but operation across multiple frequencies becomes limited
Solution Approach 1:
The patent introduces a switchable configuration that allows the system to dynamically transition between resonant mode (for low power consumption) and conventional mode (for frequency flexibility). The switchable connection between the inductor and clock node enables adaptive operation across different frequencies while maintaining low power consumption when operating at the resonant frequency
3Productivity
If transistor on-resistance is reduced to improve switching efficiency, then clocking efficiency improves, but leakage current increases
Solution Approach 1:
The patent uses high impedance voltage sources as intermediaries between the clock node and the transistor gates. These high impedance sources provide the necessary gate voltages to reduce transistor on-resistance while minimizing the capacitive loading effect, thereby reducing leakage current and improving overall switching efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces power consumption by minimizing leakage and capacitive loading, allowing for improved efficiency in both resonant and conventional modes of operation while maintaining reliability constraints.
Implementation Method 1
The inductor forms a resonant circuit with capacitance of a clock system when the switch is closed
Data Source
AI summary
A clock system of an integrated circuit includes first and second transistors forming a switch that is used when switching the clock system between a resonant mode of operation and a non-resonant mode of operation. An inductor forms a resonant circuit with capacitance of the clock system in resonant mode. The switch receives a clock signal and supplies the clock signal to the inductor when the switch is closed and disconnects the inductor from the clock system when the switch is open. First and second high impedance voltage sources supply respective first and second voltages to the switch and a gate voltage of the first transistor transitions with the clock signal around the first voltage and a gate voltage of the second transistor transitions with the clock signal around the second voltage such that near constant overdrive voltages are maintained for the first and second transistors.