Two-Way Clock Switch With Edge-Synchronized Glitch Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock switching technologies in electronic devices often experience glitches when switching between clock signals, particularly due to asynchronous RESET pulses and synchronization issues, which can lead to undefined initial states and errors during power-up.
Innovation Solution
A clock switch system utilizing a control stage with feedback from the multiplexer control signal and clock selection signal to manage tristate buffers, ensuring synchronized switching and preventing glitches by using logical AND operations and delayed tristate buffers with regenerative loops to maintain output signals during transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional clock switch uses asynchronous RESET pulse and simple multiplexer control, then the device can be powered up quickly, but clock switching glitches occur and undefined initial states are generated
Solution Approach 1:
The patent implements feedback by using the multiplexer control signal itself as an input to the control stage. The control stage continuously monitors the current state of the multiplexer control signal and compares it with the desired state from the clock selection signal, enabling automatic state management and glitch prevention without external intervention
Solution Approach 2:
The control stage proactively manages the transitions of the multiplexer control signal before glitches can occur. By using the feedback from the current control signal state, the control stage prepares and executes synchronized switching operations that prevent undefined states from occurring in the first place
2Speed
If the multiplexer control signal switches immediately in response to clock selection signal, then the switching speed is fast, but glitches occur when switching coincides with clock edges
Solution Approach 1:
The control stage uses feedback from the multiplexer control signal to detect the current state and synchronize transitions with clock edges. This feedback mechanism allows the system to maintain fast switching while avoiding glitches by coordinating control signal changes with the clock signal timing
Solution Approach 2:
The control stage dynamically adjusts the timing of multiplexer control signal transitions based on the clock signal state. Rather than fixed timing, the system adapts its switching behavior to the dynamic state of the clock signal, enabling fast switching without glitch generation
3Use of energy by moving object
If tristate buffers are switched to high impedance mode during clock switching, then power consumption is reduced, but output signal instability occurs during transitions
Solution Approach 1:
The control stage uses feedback to coordinate the switching of tristate buffers with the multiplexer control signal. This ensures that buffers transition to high impedance mode only when the multiplexer has already selected the appropriate input, maintaining output stability while achieving power savings
Data Source
AI summary
The present invention switches between a first clock signal (CLK0) and a second clock signal (CLK1). Each input signal is buffered by a corresponding tristate buffer (TBUF0, TBUF1). A multiplexer (MUX) receives the tristate buffer outputs and selects one clock signal in response to a multiplexer control signal (MUX_SEL). A control stage (CONTROL) received a clock selection signal (SEL) and provides multiplexer control signal (MUX_SEL). A change in multiplexer control signal (MUX_SEL) is triggered by a next edge of target clock (CLK1) following a delay. This prevents glitches in the output signal.