Glitch-Free Clock Switch-Over Circuit for FPGA Routing
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Solution Overview
Problem
Conventional clock switch-over circuits in FPGAs are inflexible and cannot be configured to satisfy specific FPGA circuit design requirements, limiting their ability to switch between different clock signals without causing glitches in the clock routing network.
Innovation Solution
A clock switch-over circuit that includes a multiplexer to select between multiple clock signals based on a switch select signal, with a storage circuit to enable or disable the clock signal, and a logic circuit to transmit the output clock signal to a clock routing network, ensuring glitch-free switching by synchronizing the enable signal with the clock edge using flip-flops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional clock switch-over circuit with a fixed multiplexer and enable register is used, then the circuit structure is simple, but the circuit cannot be configured to satisfy specific FPGA design requirements
Solution Approach 1:
The clock switch-over circuit is divided into multiple configurable components: a multiplexer for clock signal selection, an enable register for clock enable/disable control, and a logic circuit for glitch-free switching. Each component can be independently configured to meet specific design requirements, allowing the overall circuit to be adapted to different FPGA applications while maintaining manageable complexity through modular organization.
2Reliability
If clock switching is performed without proper synchronization, then the switching speed is fast, but glitches and meta-stability issues occur in the clock routing network
Solution Approach 1:
The enable register is configured to synchronize the clock enable signal with the clock edge before switching occurs. This preliminary synchronization ensures that the clock signal is properly stabilized and ready for switching, preventing glitches and meta-stability issues in the clock routing network while maintaining efficient switching performance.
3Adaptability or versatility
If a fixed clock switch-over circuit is used, then the device complexity is low, but the circuit cannot support various clock switch-over features and configurations
Solution Approach 1:
The clock switch-over circuit is designed with universal components that can perform multiple functions: the multiplexer can select between different clock sources, the enable register can control clock enable/disable timing, and the logic circuit can implement glitch-free switching. This multi-functional design allows a single circuit structure to support various clock switch-over features and configurations required by different FPGA designs without requiring separate dedicated circuits for each function.
Data Source
AI summary
Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.