Redundant Clock Switching with Phase-Aligned Delay Control
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Solution Overview
Problem
Clock signal failures in digital electronic systems, such as phase and frequency variations or complete loss, can lead to system downtime and data integrity issues, especially in mid-range and high-end computing systems, and switching between redundant clock sources may introduce signal glitches and jitter.
Innovation Solution
A redundant clock switch circuit with delay circuits and control logic maintains phase alignment between redundant clock signals, allowing seamless switching without introducing phase errors or glitches, using clock detect circuits and a phase detector to adjust delays and prevent signal anomalies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two independent clock signal sources are used with a switch circuit, then clock signal reliability is improved, but signal glitches and phase errors are introduced during switching
Solution Approach 1:
The patent applies preliminary action by pre-aligning the phases of both clock signals before switching occurs. The phase alignment circuit continuously adjusts the phase of the second clock signal to match the first clock signal, so that when switching happens, both signals are already in phase, preventing glitches and phase errors in the output
Solution Approach 2:
The patent uses a phase alignment circuit as an intermediary between the two independent clock sources and the switch circuit. This intermediary component actively monitors and adjusts the phase relationship between clock signals, mediating the potential harmful effects of phase differences during switching operations
2Manufacturing precision
If a phase-locked loop (PLL) circuit is used to correct phase differences, then phase alignment is improved, but additional jitter and cascaded PLL stability problems are introduced
Solution Approach 1:
The patent extracts the phase alignment function from the complex PLL circuit and implements it through a simpler dedicated phase alignment circuit. This separates the phase adjustment function from frequency multiplication and other PLL functions, eliminating the additional jitter and stability issues that come with using a full PLL circuit for phase alignment
Solution Approach 2:
The patent replaces the expensive and complex PLL circuit with a simpler, more straightforward phase alignment circuit that achieves the same phase alignment goal without the adverse side effects. The simpler circuit design avoids the cascaded stability problems and additional jitter inherent in PLL-based solutions
3Adaptability or versatility
If clock signals with slightly different frequencies are switched, then redundancy is maintained, but phase misalignment and signal anomalies occur
Solution Approach 1:
The patent applies dynamics by making the phase alignment adjustable and adaptive rather than fixed. The phase alignment circuit can dynamically adjust the phase of the second clock signal in real-time to track changes in frequency and phase relationship, maintaining alignment even when the two clock sources have slightly different frequencies
Solution Approach 2:
The patent changes the phase parameter of the second clock signal dynamically to maintain alignment with the first clock signal. By adjusting the phase parameter in response to frequency differences, the system maintains signal stability while preserving the redundancy of having two independent clock sources with slightly different frequencies
Data Source
AI summary
A redundant clock switch circuit that includes two delay circuits and control logic is presented. The first delay circuit is configured to delay a first clock signal to produce a first delayed clock signal, while the second delay circuit is configured to delay a second clock signal to produce a second delayed clock signal. The control logic is configured to control the delay circuits to maintain phase alignment between the first and second delayed clock signals. The control logic is also configured to select one of the first and second delayed clock signals as an output clock signal.